Semiconductor booster circuit having cascaded MOS transistors

ABSTRACT

A semiconductor booster circuit includes: a plurality of stages, each having a first MOS transistor and a first capacitor having one terminal connected to a drain terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors of the stages in cascade; and at least one of a first arrangement wherein a source terminal of the first MOS transistor of each of the stages is electrically connected to its substrate, and the substrates of the first MOS transistors in the plurality of stages are electrically insulated from one another, and a second arrangement wherein one terminal of a second capacitor is connected to a gate terminal of the first MOS transistor of each of the stages, and a first clock signal generating unit for inputting a first clock signal to the other terminal of the first capacitor in each stage and a second clock signal generating unit for inputting a second clock signal having a larger amplitude than a power supply voltage (Vdd) to the other terminal of the second capacitor, in each stage are provided.

This application is a divisional of U.S. Ser. No. 08/423,089, filed Apr.18, 1995, now pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor booster circuit andmore particularly to a semiconductor booster circuit, such as a chargepump circuit, which is used in an EEPROM (Electrically Erasable andProgrammable Read Only Memory) and a flash memory.

2. Description of the Related Art

In recent years, along with the promotion of a single 5V power supply orthe promotion of a single 3V power supply for semiconductor integratedcircuits such as EEPROMs and flash memories, the boosting has beenperformed in the integrated circuit. As a result, semiconductor boostercircuits such as a Cockcroft Walton circuit and a charge pump circuithave been employed.

FIG. 18 shows a configuration of a conventional semiconductor boostercircuit.

As shown in the figure, N-channel MOS transistors Q₂₀ to Q₂₄ areconnected in cascade to configure a booster circuit having n stages. Thegate terminals of the transistors Q₂₀ to Q₂₄ are connected to therespective source terminals N₂₀ to N₂₄ to which a clock signal φ_(A) orφ_(B) is input through respective capacitors C₂₀ to C₂₄.

As shown in FIG. 19, the clock signals φ_(A) and φ_(B) are in oppositephase with each other. Each of the clock signals φ_(A) and φ_(B) has aperiod of 1/f and an amplitude of V_(φ). The clock signals φ_(A) andφ_(B) are obtained from a clock signal CK through two NAND circuits ND₁and ND₂ and three inverters 1V₁ to 1V₃, and the amplitude V_(φ) thereofis equal to a power supply voltage Vdd. Incidentally, in FIG. 18,reference symbol G designates a ground terminal.

As shown in FIG. 18, in this semiconductor booster circuit, the powersupply voltage Vdd is output as an input signal from a source terminalN₂₇ of a transistor Q₂₅, and an output voltage V_(POUT) is output as anoutput signal from an output terminal N₂₆.

As described in an article “Analysis and Modeling of On-ChipHigh-voltage Generator Circuits for Use in EEPROM Circuits (IEEE JOURNALOF SOLID-STATE CIRCUITS, vol. 24, No. 5, October 1989) for example, theoutput voltage V_(POUT) of a sort of the semiconductor booster circuitis expressed by the following expressions:

V _(POUT) =V _(in) −V _(t) +n([V _(φ) ·[C/(C+C _(s))−V _(t) ]−I _(OUT)/f(C+C _(s))]  (1)

Vt=V _(t0) +K ₂·([Vbs+2φ_(f))^(½)−(2φ_(f))^(½)]  (2)

where V_(in) is an input of the booster circuit, V₀ is an amplitudevoltage of the clock signal, f is a clock frequency, C is a couplingcapacitance to the clock signal, Cs is a parasitic capacitance in eachof stages in the booster circuit, n is the number of stages of thebooster circuit, V_(POUT) is the output voltage in the final stage ofthe booster circuit, I_(OUT) is a load current in the output stage, Vtois a threshold voltage when a substrate bias is absent, Vbs is asubstrate bias voltage (a potential difference between the source and asubstrate or a well), φ_(f) is a Fermi potential, Vt is a thresholdvoltage of the transistor, and K₂ is a substrate bias coefficient.

From the expression (1), it is understood that when the load currentI_(OUT) is zero and the relation of C/(C+Cs)=1 is established, theoutput voltage V_(POUT) is increased in proportion to both a value of(V_(φ)−Vt) and the number n of stages of the booster circuit. In theconventional booster circuit shown in FIG. 22, since the amplitudevoltage V_(φ) of the clock signal is equal to the power supply voltageVdd, the output voltage V_(POUT) is increased in proportion to both thevalue of (Vdd−Vt) and the number of stages of the booster circuit.

However, in the conventional booster circuit, there occurs a phenomenonthat as the level of the output voltage V_(POUT) is increased, as shownin the expression (2), the threshold voltage Vt of each of thetransistors Q₂₀ to Q₂₄ is increased due to the substrate effect.

Therefore, in the case where the stages of the booster circuit arediscretely configured in order to prevent the substrate effect fromoccurring, the level of the output voltage V_(POUT) is increased inproportion to the number n of stages of the booster circuit. On theother hand, in the case where the transistors Q₂₀ to Q₂₄ are integratedto be formed on the same substrate, since the substrate effect occurs,as the number n of stages of the booster circuit is increased, the valueof (Vdd−Vt) is decreased.

As a result, as shown in FIG. 20, along with the increasing of thenumber of n of stages of the booster circuit, the output voltageV_(POUT) is decreased to a level lower than a value which is obtainedwhen no substrate effect occurs, and is saturated at the point where thevalue of (Vdd−Vt) becomes zero. This means that no matter how the numbern of stages of the booster circuit is increased, there is a limit in theresultant output voltage V_(POUT). FIG. 24 shows the relationshipbetween the power supply voltage Vdd and a maximum output voltage whenthe number n of stages of the booster circuit is made infinitely large.When the number n of stages of the booster circuit is made infinitelylarge, in the case where no substrate effect occurs, the resultantoutput voltage V_(POUT) becomes theoretically infinite. On the otherhand, in the case where the substrate effects actually occurs, theresultant output voltage V_(POUT) is limited to a value depending on thepower supply voltage Vdd. That is, in the conventional booster circuit,there arises a problem that in the case where the level of the powersupply voltage Vdd is low, the desired output voltage V_(POUT) can notbe obtained even if the number n of stages of the booster circuit is setto any large value.

For example, in the conventional booster circuit shown in FIG. 18, inthe case where the power supply voltage Vdd is 2.5V, and the thresholdvoltage Vto is 0.6V when no substrate effect occurs (the substrate biasvoltage is 0V), when the number n of stages of the booster circuit isset to 20, 20V can be obtained as the output voltage V_(POUT). However,in the case where the power supply voltage Vdd is 2.0V, even if thenumber n of stages of the booster circuit is set to 100, only 12V can beobtained as the output voltage V_(POUT).

On the other hand, in JP-A-61-254078, there is disclosed a Cockcrofttype booster circuit in which a threshold voltage Vt of a MOS transistorin the subsequent stage having the substrate effect is made lower thanthat of a MOS transistor in the preceding stage, thereby improving thereduction of the output voltage due to the substrate effect.

However, in this configuration as well, the increase of the thresholdvoltage Vt due to the substrate effect can not be suppressed. Forexample, in the case where the level of the power supply voltage Vdd isapproximately halved (Vdd=1 to 1.5V), even if the number n of stages ofthe booster circuit is set to any value, the desired output voltageV_(POUT) can not be obtained. In addition, since the threshold voltagesVt of the MOS transistors are set to a plurality of different levels,for example, it is necessary to conduct the extra process of photomaskand ion implantation. As a result, the manufacturing process becomescomplicated. This is a disadvantage.

FIG. 22 shows a configuration of still another conventionalsemiconductor booster circuit.

As shown if FIG. 22, eight N-channel MOS transistors M₁ to M₈ areconnected in series with one another to configure a booster circuithaving four stages. Gate terminals of the transistors M₁ to M_(m8) areconnected to respective drain terminals (represented by nodes N₀ to N₇).To the drain terminals N₀, N₂, N₄ and N₆, a clock signal φ_(A) as shownin FIG. 17 is input through capacitors C₁, C₃, C₅ and C₇, respectively.To the drain terminals N₁, N₃, N₅ and N₇, a clock signal φ_(B) which isin opposite phase with the clock signal φ_(A) is input throughcapacitors C₂, C₄, C₆ and C₈, respectively. In addition, substrateterminals of the transistors M₁ to M₈ are connected to a ground terminal(represented by a node N₂₁). In addition, both a drain terminal and agate terminal of each of the N-channel MOS transistors M₂₀ and M₂₁ areconnected to an associated input terminal (represented by a node N₂₀),and a substrate terminal thereof is connected to the ground terminalN₂₁.

That is, the node N₀ is respectively connected to the source terminal ofthe transistor M₂₀, both the drain terminal and the gate terminal of thetransistor M₁, and one terminal of the capacitor C₁. The node N₁ isrespectively connected to the source terminal of the transistor M₂₁,both the drain terminal and the gate terminal of the transistor M₂, thesource terminal of the transistor M₁ and one terminal of the capacitorC₂. The node N₂ is respectively connected to both the drain terminal andthe gate terminal of the transistor M₃, the source terminal of thetransistor M₂ and one terminal of the capacitor C₃. The node N₃ isrespectively connected to both the drain terminal and the gate terminalof the transistor M₄, the source terminal of the transistor M₃ and oneterminal of the capacitor C₄. The node N₄ is respectively connected toboth the drain terminal and the gate terminal of the transistor M₅, thesource terminal of the transistor M₄ and one terminal of the capacitorC₅. The node N₅ is respectively connected to both the drain terminal andthe gate terminal of the transistor M₆, the source terminal of thetransistor M₅ and one terminal of the capacitor C₆. The node N₆ isrespectively connected to both the drain terminal and the gate terminalof the transistor M₇, the source terminal of the transistor M₆ and oneterminal of the capacitor C₇. In addition, the node N₇ is respectivelyconnected to both the drain terminal and the gate terminal of thetransistor M₈, the source terminal of the transistor M₇ and one terminalof the capacitor C₈. Further, an output terminal (represented by a nodeN₈) of the semiconductor booster circuit is connected to the sourceterminal of the MOS transistor M₈.

The above-mentioned expressions (1) and (2) are also applied to thisbooster circuit. Then, if the load current I_(OUT) is zero, thecapacitance ratio C/(C+Cs) is 1, and the amplitude voltage V_(φ) of theclock signal is equal to the power supply voltage Vdd in the expression(1), the voltage which is boosted per stage is expressed by (Vdd−Vt).

Therefore, it is understood that the output voltage V_(POUT) isinfluenced by the margin between the threshold voltage Vt of each of theMOS transistors and the power supply voltage Vdd. In particular, it isunderstood that when the relation of Vt≧Vdd is established, the boostingoperation is not performed in the corresponding stage. That is, if thethreshold voltage Vt is increased, the voltage which is boosted perstage becomes either small or zero. Therefore, even if the number n ofstages of the booster circuit is increased, the output voltage V_(POUT)is hardly or never increased. For example, since the source potential ofthe MOS transistor shown in FIG. 22 is equal to the output voltageV_(POUT), and the substrate potential is 0V, the substrate bias voltageVbs is equal to the output voltage V_(POUT). Now, since the boostercircuit shown in FIG. 22 is provided for generating the positive highvoltage, the output voltage V_(POUT) takes one of positive values.Therefore, the threshold voltage of the MOS transistor M₈ becomes veryhigh, and hence the boosting efficiency is reduced. This problem becomesespecially pronounced during the low power source voltage operation inwhich the margin between the threshold voltage Vt and the power supplyvoltage Vdd is small.

In this booster circuit, as shown in FIG. 22, all the substrateterminals of the MOS transistors M₁ to M₈ are grounded. That is, the MOStransistors M₁ to M₈ are, as shown in FIG. 23, respectively constitutedby sources/drains 454 to 462, which are formed in a P type semiconductorsubstrate 451, and gates 464 to 471, and the substrate terminal isconnected to a ground terminal N₂₁ through a P⁺ type impurity diffusionlayer 452 in the semiconductor substrate 451. Incidentally, referencenumeral 453 designates a drain of a MOS transistor 20 and referencenumeral 463 designates a gate of the MOS transistor 20.

Therefore, there arises a problem that the potential of the sourceterminal of the MOS transistor, which is located in the more backwardstage, becomes higher, and the difference in the potential between thesource terminal and the substrate portion is increased so that due tothe so-called substrate bias effect, the threshold voltage Vt isincreased, and hence the output voltage V_(POUT) is limited due to theincrease of the threshold voltage Vt.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asemiconductor booster circuit in which a desired output voltage iscapable of being obtained, even in the case where a level of a powersupply voltage is low, without the necessity of the complicatedmanufacturing process.

A semiconductor booster circuit, according to the present invention,includes: a plurality of stages, each having a first MOS transistor anda first capacitor having one terminal connected to a drain terminal ofthe first MOS transistor, the stages being connected in series byconnecting the first MOS transistors of the stages in cascade; and atleast one of a first arrangement wherein a source terminal and asubstrate of the first MOS transistor of each of the stages areelectrically connected to each other and when the plurality of stagesare divided into at least two groups, the substrates of the first MOStransistor included in each group are electrically insulated from thesubstrates of the first MOS transistors included in a different groupand an arrangement wherein one terminal of a second capacitor isconnected to a gate terminal of the first MOS transistor of each of thestages, and first clock signal generating means for inputting a firstclock signal to the other terminal of the first capacitor, and secondclock signal generating means for inputting a second clock signal havinga larger amplitude than a power supply voltage to the other terminal ofthe second capacitor are provided.

The semiconductor booster circuit, according to a first aspect of thepresent invention, includes a plurality of stages, each having a firstMOS transistor and a first capacitor having one terminal connected to adrain terminal of the MOS transistor, the stages being connected inseries by connecting the MOS transistors of the stages in cascadewherein a source terminal and a substrate of the first MOS transistor ofeach of the stages are electrically connected to each other and when theplurality of stages are divided into at least two groups, the substratesof the first MOS transistors included in each group are electricallyinsulated from the substrates of the first MOS transistors included in adifferent group.

In one embodiment of the present invention, the first MOS transistor isa P-channel MOS transistor which is formed in an N type well region, andthe N type well regions of the respective stages are electricallyinsulated from one another.

In one embodiment of the present invention, in each of the stages, asecond capacitor having one terminal, which is connected to a gateterminal of the first MOS transistor, is provided, and also the gateterminal and the source terminal of the first MOS transistor areconnected to each other through a second MOS transistor, and a gateterminal of the second MOS transistor is connected to the one terminalof the first capacitor.

In one embodiment of the present invention, a pair of first clocksignals which are in opposite phase with each other are respectivelyinputted to the two other terminals of the first capacitors in the twocontinuous stages, and a pair of second clock signals which aredifferent in pulse timing from each other are respectively inputted tothe two other terminals of the second capacitors in the two continuousstages.

In one embodiment of the present invention, in each of the stages, thegate terminal of the first MOS transistor in the preceding stage isconnected to the one terminal of the first capacitor in the subsequentstage, and a pair of clock signals which are in opposite phase with eachother are respectively inputted to the two other terminals of the firstcapacitors in the two continuous stages.

In one embodiment of the present invention, each of the stages includesa first MOS transistor and a first capacitor having one terminalconnected to a source terminal of the first MOS transistor, wherein thestages are connected in series by connecting the first MOS transistorsof the respective stages in cascade, a gate terminal and the sourceterminal of the first MOS transistor in each stage are electricallyconnected to each other, and also the source terminal and the substratethereof are electrically connected to each other and the substrate iselectrically insulated from the substrate of the first MOS transistorsin another stage.

Incidentally, in a preferred aspect of the present invention, the firstMOS transistor is an N-channel MOS transistor which is formed in a Ptype well region, and the P type well regions of the respective stagesare electrically insulated from one another.

In the first aspect of the present invention, the substrate of the MOStransistor forming each of the stages of the booster circuit iselectrically insulated from the substrate of the MOS transistor ofanother stage, and in each of the stages, the substrate and the sourceterminal of the MOS transistor are electrically connected to each other,whereby the potential at the substrate of the MOS transistor is fixed tothe source potential. Hence the increase of the threshold voltage of theMOS transistor due to the substrate effect is effectively suppressed.

A semiconductor booster circuit, according to a second aspect of thepresent invention, includes: a plurality of stages, each having a firstMOS transistor, a first capacitor having one terminal connected to adrain terminal of the first MOS transistor, and a second capacitorhaving one terminal connected to a gate terminal of the first MOStransistor, the stages being connected in series by connecting the firstMOS transistors in the respective stages in cascade; first clock signalgenerating means for inputting a first clock signal to the otherterminal of the first capacitor and second clock signal generating meansfor inputting a second clock signal having a larger amplitude than apower supply voltage to the other terminal of the second capacitor.

In one embodiment of the present invention, the first clock signalincludes a pair or clock signals which are in opposite phase with eachother, and the pair of clock signals are respectively inputted to thetwo first capacitors in the two consecutive stages.

In one embodiment of the present invention, in each of the stages, thegate terminal and the drain terminal of the first MOS transistor areconnected to each other through a second MOS transistor, and a gateterminal of the second MOS transistor is connected to the other terminalof the first capacitor in the subsequent stage.

In the second aspect of the present invention, in order to drive the MOStransistors to perform the boosting operation, other clock signals areemployed which are different from the clock signals which are used todrive the stages and have a larger amplitude than the power supplyvoltage, whereby it is possible to secure the threshold for conductingthe MOS transistor and also it is possible to prevent the reduction ofthe output voltage due to the substrate effect.

A semiconductor booster circuit, according to a third aspect of thepresent invention, includes: a plurality of stages, each having a firstMOS transistor and a first capacitor having one terminal connected to adrain terminal of the first MOS transistor, the stages being connectedin series by connecting the first MOS transistors of the respectivestages in cascade, wherein a source terminal and a substrate of thefirst MOS transistor in each of the stages are electrically connected toeach other, and when the plurality of stages are divided into at leasttwo stages, the substrates of the first MOS transistors included in eachgroup are electrically insulated from the substrates of the first MOStransistors included in another group; and wherein one terminal of asecond capacitor is connected to a gate terminal of the first MOStransistor in each of the stages, and first clock signal generatingmeans for inputting a first clock signal to the other terminal of thefirst capacitor in each stage, and second clock signal generating meansfor inputting a second clock signal having a larger amplitude than apower supply voltage to the other terminal of the second capacitor ineach stage are provided.

In one embodiment of the present invention, the first MOS transistor isa P-channel MOS transistor which is formed in an N type well region, andthe N type well regions in the respective stages are electricallyinsulated from one another.

In one embodiment of the present invention, in each of the stages, thegate terminal and the source terminal of the first MOS transistor areelectrically connected to each other through a second MOS transistor,and a gate terminal of the second MOS transistor is connected to the oneterminal of the first capacitor.

In one embodiment of the present invention, the first clock signalincludes a pair of clock signals which are in opposite phase with eachother, and the pair of clock signals are respectively inputted to thefirst capacitors in the two consecutive stages.

In the third aspect of the present invention, the substrate of the MOStransistor constituting each of the stages of the booster circuit iselectrically insulated from the substrate of the MOS transistor inanother stage, and also in each of the stages, the substrate and thesource terminal of the MOS transistor are electrically connected to eachother, whereby the potential at the substrate of the MOS transistor isfixed to the source potential. Hence the increase of the thresholdvoltage of the MOS transistor due to the substrate effect is suppressed.

In addition, the gate voltage of the MOS transistor which operates toperform the boosting operation in the stages is controlled by the clocksignals other an the source voltage and the drain voltage, and theamplitude of each of the clock signals is made larger than the inputpower supply voltage of the booster circuit, whereby since even in theemployment of the low power supply voltage, the MOS transistor can besufficiently rendered to an on state, and also the voltage drop due tothe threshold voltage of the MOS transistor is eliminated so that theboosting capability is improved.

A semiconductor booster circuit, according to a fourth aspect of thepresent invention, includes a plurality of stages, each of the stageshaving two first MOS transistors which are connected in series with eachother and two capacitors, each having one terminal connected to a drainor source terminal of one of the first MOS transistors, the seriescircuits of the first MOS transistors of the respective stages beingconnected in series between an input side and an output side, whereinthe plurality of stages are divided into at least two groups, andsubstrates of the first MOS transistors included in the stages of eachgroup are formed integrally in a conductive substrate portion, and thepotentials which are applied to the substrate portions of the groups arecontrolled independently of one another.

In one embodiment of the present invention, the booster circuit operatesfor generating a positive high voltage and the substrate portions of thefirst MOS transistors included in the more backward stage are controlledat a higher potential.

In one embodiment of the present invention, the first MOS transistor isa P-channel MOS transistor which is formed in an N type well region, andthe N type well regions of the respective groups are electricallyinsulated from one another.

In one embodiment of the present invention, the booster circuit operatesfor generating a negative high voltage and the substrate portions of thefirst MOS transistors included in the more backward stage are controlledat a negative lower potential.

In one embodiment of the present invention, the first MOS transistor isan N-channel MOS transistor which is formed in a P type well region, andthe P type well regions of the respective groups are electricallyinsulated from one another.

In one embodiment of the present invention, the substrate of the firstMOS transistor of each stage is connected to a drain terminal or asource terminal of the first MOS transistor which is located at thepreceding stage of the group to which the first MOS transistor belongs.

In one embodiment of the present invention, second capacitors eachhaving one terminal connected to the gate terminal of one of the firstMOS transistors are provided, and the gate terminal and the source ordrain terminal of each of the first MOS transistors are connected toeach other through a second MOS transistor, and the gate terminal of thesecond MOS transistor is connected to the one terminal of the firstcapacitor.

In one embodiment of the present invention, in each of the stages, thesubstrate of the second MOS transistor is connected to the substrate ofthe first MOS transistor.

In one embodiment of the present invention, a pair of first clocksignals which are in opposite phase with each other are respectivelyinputted to the other terminals of the two adjacent first capacitors,and also a pair of second clock signals which are different in pulsetiming from each other are respectively inputted to the other terminalsof the two adjacent second capacitors.

In the fourth aspect of the present invention, since the substrateportions of the MOS transistors constituting the booster circuit aredivided into groups and the potentials of the substrate portions in therespective groups are controlled independently of one another, thepotentials at the substrate portions of the MOS transistors of eachgroup can be fixed to a potential different from that of another group.Therefore, it is possible to suppress the increase of the thresholdvoltage of the MOS transistor due to the substrate bias effect, and alsothe level of the output voltage can be made higher than that in theconventional booster circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a first embodiment of the presentinvention;

FIG. 2 is a circuit diagram showing a configuration of the twocontinuous stages of the semiconductor booster circuit according to thefirst embodiment shown in FIG. 1;

FIG. 3 is a timing chart showing the timing of clock pulses used in thesemiconductor booster circuit shown in FIG. 1;

FIGS. 4A to 4D are respectively graphical representations showingwaveforms of voltages at respective nodes of the semiconductor boostercircuit shown in FIG. 1;

FIGS. 5A to 5F are respectively circuit diagrams useful in explainingthe operation of the semiconductor booster circuit shown in FIG. 1;

FIG. 6 is a cross sectional view showing a device structure of thesemiconductor booster circuit shown in FIG. 1;

FIG. 7 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a second embodiment of the presentinvention;

FIG. 8 is a timing chart showing clock pulses used in the semiconductorbooster circuit shown in FIG. 6;

FIG. 9 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a third embodiment of the presentinvention;

FIG. 10 is a cross sectional view showing a device structure of thesemiconductor booster circuit shown in FIG. 9;

FIG. 11 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a fifth embodiment of the presentinvention;

FIG. 12 is a timing chart showing clock pulse used in the semiconductorbooster circuit shown in FIG. 11;

FIG. 13 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a sixth embodiment of the presentinvention;

FIG. 14 is a cross sectional view showing a device structure of thesemiconductor booster circuit shown in FIG. 13;

FIG. 15 is a circuit diagram showing a configuration of a semiconductorbooster circuit according to a seventh embodiment of the presentinvention;

FIG. 16 is a timing chart showing clock pulses used in the semiconductorbooster circuit shown in FIG. 13;

FIG. 17 is a timing chart showing clock pulses used in the semiconductorbooster circuit shown in FIG. 15;

FIG. 18 is a circuit diagram showing a configuration of a conventionalsemiconductor booster circuit;

FIG. 19 is a timing chart showing clock pulses used in the conventionalprior art semiconductor booster circuit;

FIG. 20 is a graphical representation showing the relationship betweenthe number of stages and an output voltage of the conventional prior artsemiconductor booster circuit;

FIG. 21 is a graphical representation showing the relationship between apower supply voltage and a maximum output voltage when the number ofstages of the conventional prior art semiconductor booster circuit isinfinite;

FIG. 22 is a circuit diagram showing a configuration of anotherconventional prior art semiconductor booster circuit; and

FIG. 23 is a cross sectional view showing a device structure of anotherconventional prior art semiconductor booster circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of the present invention will hereinafter bedescribed in detail with reference to FIGS. 1 to 10.

FIG. 1 shows a configuration of a semiconductor booster circuitaccording to the first embodiment of the present invention.

As shown in FIG. 1, n elements of P-channel MOS transistors Q₁, Q₃, Q₅,Q₇, . . . , Q₉ are connected in cascade to configure a booster circuithaving n stages. Substrate portions of the transistors Q₁, Q₃, Q₅, Q₇, .. . , Q₉ are electrically insulated from one another and also areconnected to source terminals of the transistors Q₁, Q₃, Q₅, Q₇, . . . ,Q₉, respectively. In addition, to drain terminals (represented by nodesN₁, N₃, N₅, N₇, . . . , N₉) a clock signal φ₁ _(^(A)) or φ₁ _(^(B))which is shown in FIG. 3 is inputted through respective capacitors C₁,C₃, C₅, C₇, . . . , C₉.

In addition, to gate terminals (represented by nodes N₂, N₄, N₆, N₈, . .. , N₁₀) of the transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉, a clock signalφ_(2A) or φ_(2B) which is shown in FIG. 3 is inputted through respectivecapacitors C₂, C₄, C₆, C₈, . . . , C₁₀.

Further, P-channel MOS transistors Q₂, Q₄, Q₅, Q₈, . . . , Q₁₀ arerespectively connected between the gate terminals N₂, N₄, N₆, N₈, . . ., N₁₀ and source terminals (represented by nodes N₃, N₅, N₇, N₁₁, . . ., N₁₂) of the transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉, and gate terminalsof the transistors Q₂, Q₄, Q₆, Q₈, . . . , Q₁₀ are respectivelyconnected to the drain terminals N₁, N₃, N₅, N₇, . . . , N₉ of thetransistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉.

In the booster circuit of the present embodiment, a power supply voltageVdd is inputted as an input signal from a common source terminal(represented by a node N₀) of N-channel MOS transistors Q₁₂ and Q₁₃ tothe source terminals N₁ and N₃ of the transistors Q₁ and Q₃, and anoutput voltage V_(POUT) is outputted as an output signal from an outputterminal (represented by a node N₁₃) through an N-channel MOS transistorQ₁₁. As shown in the figure, the gate terminals of the transistors Q₁₂and Q₁₃ are respectively connected to the source terminal N₀. Inaddition, to a source terminal (represented by a node N₁₂) of thetransistor Q₁₁, the clock signal φ_(1A) which is shown in FIG. 3 isinputted through a capacitor C₁₁. Further, a gate terminal of thetransistor Q₁₁ is connected to a drain terminal (represented by the nodeN₁₃).

As shown in FIG. 3, the clock signals φ_(1A) and φ_(1B) are in oppositephase with each other and have the same amplitude as the power supplyvoltage Vdd, and the clock signals φ_(2A) and φ_(2B) are pulse-likesignals which have the amplitude equal to or larger than the powersupply voltage Vdd and are in an off-state at periods when the clocksignals φ_(1A) and φ_(1B) are in an on-state, respectively.

As for a clock signal generating unit 120 which operates to generate theclock signals φ_(1A) and φ_(1B), the same as the conventional unit maybe employed. As for clock signal generating units 140 and 160 whichoperate to generate the clock signals φ_(2A) and φ_(2B), respectively,any units may be employed which operate to receive clock pulse signalsCLK₂ and CLK₃ of the same timings as those of the generating timings ofthe clock signals φ_(2A) and φ_(2B), respectively, and control theamplitudes thereof.

Next, the description will hereinbelow be given with respect to theoperation of the semiconductor booster circuit according to the firstembodiment with reference to FIGS. 2 to 5.

FIG. 2 is a circuit diagram showing a configuration of two consecutivestages (a first stage and a second stage) of the semiconductor boostercircuit shown in FIG. 1. In addition, FIGS. 4A to 4D show waveforms ofthe voltages at nodes N_(A) to N_(D) of the circuit of FIG. 2 for a timeperiod ranging from (I) to (VI) shown in FIG. 3. Further, FIGS. 5A to 5Fare respectively circuit diagrams useful in explaining the conductionstate of transistors M₁ to M₄ of FIG. 2 for a time period ranging from(I) to (VI).

Firstly, for a period of time of (I), as shown in FIG. 3, the level ofthe clock signal φ_(1A) is raised from the ground potential up to thepower supply voltage Vdd, and also the potential at the drain terminalN_(A) of the transistor M₁ shown in FIG. 2 is, as shown in FIG. 4A,raised by a voltage corresponding to the power supply voltage Vdd.

At the same time, the level of the clock signal φ_(1B) is dropped fromthe power supply voltage Vdd down to the ground potential 0V, an alsothe potential at the source terminal N_(B) of the transistor M₁ is, asshown in FIG. 4B, dropped by a voltage corresponding to the power supplyvoltage Vdd.

At this time, the electric charges which have been transferred from thepreceding stage are accumulated in the capacitor C_(A2) which isconnected to the source terminal N_(B) of the transistor M₁, and hencethe potential at the source terminal N_(B) of the transistor M₁ israised by a voltage corresponding to the electric charges accumulated inthat capacitor C_(A2).

In addition, the potential at the gate terminal N_(A) of the transistorM₂ becomes higher than that at the source terminal N_(B), and hence thetransistor M₂ is, as shown in FIG. 5A, switched from the on state to theoff state.

At this time, as will be described later, since the P_(N) junction whichis formed between the drain terminal N_(A) and the source terminal N_(B)of the transistor M₁ is biased in the forward direction, the substrateportion of the transistor M₁ which is connected to the source terminalN_(B) is maintained at the potential which is obtained by subtractingthe forward bias voltage across the P_(N) junction from the potential atthe drain terminal N_(A).

In addition, as shown in FIG. 4C, the potential at the gate terminalN_(C) of the transistor M₁ is dropped down to the same potential as thatat the drain terminal N_(A), but the transistor M₁ remains, as shown inFIG. 5A, in the off state.

As the level of the clock signal φ_(1A) is raised from the groundpotential 0V up to the power supply voltage Vdd, the potential at thesource terminal N_(D) of the transistor M₃ is, as shown in FIG. 4D,raised by a voltage corresponding to the power supply voltage Vdd.

At this time, the electric charges which have been transferred from thepreceding stage are accumulated in the capacitor C_(A3), and hence thepotential at the source terminal N_(D) of the transistor M₃ is raised bya voltage corresponding to the electric charges accumulated in thecapacitor C_(A3).

In addition, at the time when the level of the clock signal φ_(1B) hasbeen dropped from the power supply voltage Vdd down to the groundpotential 0V, the potential at the gate terminal N_(B) of the transistorM₄ is dropped and hence the transistor M₄ is switched from the off stateto the on state. Therefore, the potential at the gate terminal N_(E) ofthe transistor M₃ becomes the same potential as that at the sourceterminal N_(D) of the transistor M₃. At this time, as shown in FIG. 5A,the transistor M₃ remains in the off state.

Next, for a period of time (II), the level of the clock signal φ_(2A) isdropped from the power supply voltage Vdd down to the ground potential0V, and hence the potential at the gate terminal N_(C) of the transistorM₁ is, as shown in FIG. 4C, dropped by a voltage corresponding to thepower supply voltage Vdd.

As a result, as shown in FIG. 5B, the transistor M₁ is turned on andhence a current is caused to flow from the drain terminal N_(A) to thesource terminal N_(B) of the transistor M₁ until the potential at thedrain terminal N_(A) becomes equal to that at the source terminal N_(B).

That is, the electric charges are transferred from the capacitor C_(A1)to the capacitor C_(A2), and hence the potential at the drain terminalN_(A) of the transistor M₁ is, as shown in FIG. 4A, dropped, and alsothe potential at the source terminal N_(B) of the transistor M₁ is, asshown in FIG. 4B, raised.

In addition, with respect to the source terminal N_(D) of the transistorM₃ as well, in the same manner as that in the case of the drain terminalN_(A) of the transistor M₁, as shown in FIG. 4D, the potential at thesource terminal N_(D) is dropped.

At this time, the clock signal φ_(2A) which is used to turn thetransistor M₁ on is supplied from the outside through the capacitorC_(B1), and no voltage drop occurs between the drain terminal N_(A) andthe source terminal N_(B) when turning the transistor M₁ on. Therefore,as compared with the prior art, the boosting capability is furtherimproved. That is, in the above-mentioned expression (1), this statecorresponds to the situation in which in the term within the brackets,Vt is equal to 0V. Thus, the boosting operation can be performed with anexceptionally good efficiency.

Next, for a period of time (III), the level of the clock signal φ_(2A)is raised from the ground potential 0V up to the power supply voltageVdd, and hence the potential at the gate terminal N_(C) of thetransistor M₁ is, as shown in FIG. 4C, raised by a voltage correspondingto the power supply voltage Vdd.

As a result, as shown in FIG. 5C, the transistor M₁ is turned off.

In addition, as shown in FIGS. 4A, 4B and 4D, the potential at the drainterminal N_(A) and the source transistor N_(B) of the transistor M₁, andthe potential at the source terminal N_(D) of the transistor M₃ do notchange.

Next, for a period of time (IV), the level of the clock signal φ_(1A) isdropped from the power supply voltage Vdd down to the ground potential0V, and hence the potential at the drain terminal N_(A) of thetransistor M₁ is forced to drop by a voltage corresponding to the powersupply voltage Vdd. However, in the first stage, since the transistorQ₁₂ shown in FIG. 1 goes to the on state, as shown in FIG. 4A, thepotential at the drain terminal N_(A) of the transistor M₁ goes to thepotential of (Vdd−Vt).

In addition, the level of the clock signal φ_(1B) is raised from theground potential 0V up to the power supply voltage Vdd, and hence thepotential at the source terminal N_(B) of the transistor M₁ is, as shownin FIG. 4B, raised by a voltage corresponding to the power supplyvoltage Vdd.

At this time, since the electric charges which have been transferredfrom the preceding stage are accumulated in the capacitor C_(A2), thepotential at the source terminal N_(B) of the transistor M₁ is raised bya voltage corresponding to the electric charges accumulated in thecapacitor C_(A2).

In addition, the potential at the gate terminal N_(A) of the transistorM₂ becomes lower than that at the source terminal N_(B) thereof, andhence the transistor M₂ is, as shown in FIG. 5D, switched from the offstate to the on state.

As a result, the potential at the gate terminal N_(C) of the transistorM₁ is, as shown in FIG. 4C, raised up to the same potential as that atthe source terminal N_(B) of the transistor M₁.

In addition, as the level of the clock signal φ_(1A) is dropped from thepower supply voltage down to the ground potential 0V, the potential atthe source terminal N_(D) of the transistor M₃ is, as shown in FIG. 4D,dropped by a voltage corresponding to the power supply voltage Vdd.

At this time, the electric charges which have been transferred from thepreceding stage are accumulated in the capacitor C_(A3), and hence thepotential at the source terminal N_(D) is raised by a voltagecorresponding to the electric charges accumulated in the capacitorC_(A3).

As a result, the potential at the drain terminal N_(E) of the transistorM₄ becomes higher than that at the source terminal N_(D) thereof, andhence the transistor M₄ is, as shown in FIG. 5D, switched from the onstate to the off state.

In addition, in the same manner as that in the case of theabove-mentioned transistor M₁, since the PN junction which is formedbetween the drain terminal N_(B) and the source terminal N_(D) of thetransistor M₃ is biased in the forward direction, the substrate portionof the transistor M₃ connected to the source terminal N_(D) ismaintained at a voltage which is obtained by subtracting the forwardbias voltage across the PN junction from the potential at the drainterminal N_(B).

Next, for a period of time of (V), the level of the clock signal φ_(2B)is dropped from the power supply voltage Vdd down to the group potential0V, and hence the potential at the gate terminal N_(E) of the transistorM₃ is dropped by a voltage corresponding to the power supply voltageVdd.

As a result, as shown in FIG. 5E, the transistor M₃ is turned on, andalso a current is caused to flow from the drain terminal N_(B) to thesource terminal N_(D) of the transistor M₃ until the potential at thedrain terminal N_(B) becomes equal to that at the source terminal N_(D).

That is, the electric charges are transferred from the capacitor C_(A2)to the capacitor C_(A3), and hence as shown in FIG. 4B, the potential atthe drain terminal N_(B) of the transistor M₃ is dropped and also asshown in FIG. 4D, the potential at the source terminal N_(D) of thetransistor M₃ is raised.

In addition, since the transistor M₂ remains in the on state, and thepotential at the gate terminal N_(C) of the transistor M₁ is equal tothat at the drain terminal N_(B) of the transistor M₃, as shown in FIG.4C, the potential at the gate terminal NC of the transistor M₁ isdropped.

At this time, the clock signal φ_(2B) which is used to turn thetransistor M₃ on is supplied from the outside through the capacitor C₃₂,and no voltage drop occurs between the drain terminal N_(B) and thesource terminal, N_(D) when turning the transistor M₃ on. Therefore, ascompared with the prior art, the boosting capability is furtherimproved.

Next, for a period of time of (VI), the level of the clock signal φ_(2B)is raised from the ground potential 0V up to the power supply voltageVdd, and hence the potential at the gate terminal N_(E) of thetransistor M₃ is raised by a voltage corresponding to the power supplyvoltage Vdd.

As a result, as shown in FIG. 5F, the transistor M₃ goes to the offstate.

In addition, as shown in FIGS. 4A to 4D, the potentials at the nodesN_(A) to N_(D) do not change.

In the operation of prior art as described above, since the sourceterminals of the transistors M₁ to M₃ are boosted such that the sourceterminal of the transistor located in the subsequent stage becomeshigher, the substrate effect acts inherently to raise, as shown in theabove-mentioned expression (2), the threshold voltage Vt of each of thetransistors M₁ and M₃. However, in the present embodiment, as shown inFIG. 2, since the substrate portions of the transistors M₁ and M₃ areconnected to the source terminal, no substrate effect occurs, and hencethe transfer of the electric charges from the preceding stage to thesubsequent stage is effectively performed.

FIG. 6 is a schematic cross sectional view showing a device structure ofthe transistors M₁ and M₃ shown in FIG. 2.

As shown in FIG. 6, two N type well regions 11 are respectively formedin a P type semiconductor substrate 10 so as to be insulated from eachother, and in each of the N type well regions 11, there is formed a MOStransistor which includes a polycrystalline silicon layer 16, as a gateelectrode, which is formed on the substrate portion of the well 11 witha gate oxide film 15 disposed therebetween, and P⁺ type impuritydiffusion layers 12 as source/drain regions.

The P⁺ type impurity diffusion layer 12 of the source side in each ofthe transistors is electrically connected to the N type well region 11,in which the transistor is formed, through a N⁺ type impurity diffusionlayer 14, and the source of the transistor in the preceding stage isconnected to the drain of the transistor in the subsequent stage.

By adopting this structure, the potential at the N type well region 11as the substrate portion of each of the transistors is fixed to thesource potential of each of the transistors, and hence the substrateeffect can be effectively prevented from occurring.

In addition, for a period of time of (I) of FIG. 5A or (IV) of FIG. 5D,the PN junction which is formed between the P⁺ type impurity diffusionlayer 12 of the drain side and the N type well region 11 of each of thetransistors is biased in the forward direction. Then, through that PNjunction, the electric charges can be transferred from the node N_(A) tothe node N_(B) and from the node N_(B) to the node N_(D) through the Ntype well region 11 of the substrate and the N⁺ type impurity diffusionlayer 14. In this case, the voltage difference corresponding to theforward bias voltage V_(F) (normally, about 0.7V) across the PN junctionwhich is independent of the threshold voltage Vt of the MOS transistoris utilized for the boosting operation, and hence V_(F) is employedinstead of Vt in the above-mentioned expressions (1) and (2). Since theforward bias voltage V_(F) across the PN junction is not influenced bythe substrate effect, it is possible to realize the booster circuitwhich, even when the number of stages of the booster circuit isincreased, is free from the reduction of the boosting capability due tothe substrate effect.

As described above, in the semiconductor booster circuit according tothe first embodiment of the present invention, the substrate portions ofthe MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉ shown in FIG. 1 areelectrically insulated from one another, and also the substrate portionsare respectively connected to the source terminals N₃, N₅, N₇, N₁₁, . .. , N₁₂, whereby the increase of the threshold voltage Vt due to thesubstrate effect is effectively prevented. Therefore, it is possible toobtain the output voltage V_(POUT) which is increased in proportion tothe number n of stage of the booster circuit and also it is possible toprovide the semiconductor booster circuit which has the higher boostingcapability than that of the prior art.

In addition, with respect to the structure of the present embodiment, asshown in FIG. 6, the N type well regions 11 in which the respectivetransistors are formed are isolated from each other and also the N⁺ typeimpurity region 14 of each of the N type well regions 11 is electricallyconnected to the P⁺ type impurity region 12 of the source side of eachof the transistors. Thus, the process for making the threshold voltagesof the respective transistors different from one another, as in theprior art, is not required at all. Therefore, the number ofmanufacturing processes is not increased much.

In addition, the substrate portion of each transistor is electricallyconnected to the source terminal, whereby the PN junction which isformed in the boundary between the drain and the substrate portion isconnected in parallel between the source and drain of the transistor.Then, when transferring the electric charges from the preceding stage tothe subsequent stage in the booster circuit, the PN junction is biasedto the on state, whereby the potential at the substrate portion of eachtransistor can be fixed to a voltage difference corresponding to theforward bias voltage V_(F) (normally, about 0.7V) across the PNjunction. Thus, it is possible to suppress the influence of thesubstrate effect.

In addition, as shown in FIG. 5, to the gate terminals N_(C) and N_(E)of the transistors M₁ and M₃, the pair of clock signals φ_(2A) andφ_(2B) which are independent from the pair of clock signals φ_(1A) andφ_(1B) respectively inputted to the drain terminals N_(A) and N_(B), arerespectively inputted, whereby each of the transistors M₁ and M₃ can beturned on in such a way that no potential difference occurs between thesource and the drain thereof. Therefore, when transferring the electriccharges from the preceding stage to the subsequent stage in the boostercircuit, it is possible to realize the transfer of the electric chargessuch that the voltage drop does not occur which corresponds to thepotential difference between the source and the drain. Therefore, sincein the above-mentioned expression (1), the threshold voltage Vt can beregarded as zero, the boosting operation can be more efficientlyperformed as compared with the conventional booster circuit. Even thecase where the number n of stages of the booster circuit and the powersupply voltage Vdd are the same as those of the conventional boostercircuit, the larger output voltage V_(POUT) can be obtained. Inaddition, in the case where the output voltage V_(POUT) is the same asthat of the conventional booster circuit, the booster circuit of thepresent embodiment can obtain the larger load current I_(OUT).

For example, in the case where the power supply voltage Vdd is 20V, andthe number n of stages of the booster circuit is 20, assuming that thecapacitance ratio C/(C+Cs) is 0.9, the absolute value of the thresholdvoltage |Vt| is 0.6, and the load current I_(OUT) of the output stage iszero, only 20V can be obtained as the output voltage V_(POUT) in theconventional booster circuit, but in the booster circuit according tothe present embodiment, about 47V can be obtained.

In addition, in the semiconductor booster circuit according to thepresent embodiment, even in the low power supply voltage Vdd which cannot be boosted by the conventional booster circuit, the desired outputcan be obtained. In other words, in the conventional booster circuit, asshown in FIG. 25, even if the number n of stages of the booster circuitis set to any value, the maximum output voltage is limited to apredetermined value depending on the power supply voltage Vdd. However,in the semiconductor booster circuit according to the presentembodiment, such a limit is not present substantially.

For example, in the case where the power supply voltage Vdd is 2.0V,assuming that the capacitance ration C/(C+Cs) is 0.9, the absolute valueof the threshold voltage |Vt| is 0.6V, and the load current I_(OUT) inthe output stage is zero, even in the booster circuit in which thenumber n of stages of the booster circuit is 50, only 12V can beobtained as the output voltage V_(POUT) in the conventional boostercircuit. In the booster circuit according to the present embodiment,when the number n of stages of the booster circuit is 20, about 37V canbe obtained as the output voltage V_(POUT), and also when the number nof stages of the booster circuit is 50, about 91V can be obtained.

Incidentally, in the semiconductor booster circuit according to thepresent embodiment, in the case where the absolute value of thethreshold voltage |Vt| is set to 0.6V, the lower limit of the boostablepower supply voltage Vdd is about 0.7V.

In the above explanation, the substrates of the MOS transistors in nstages are electrically insulated from each other. Alternatively, the nstages are divided into at least two groups, for example two groups i.e.a first group of the first to third stages and a second group of thefourth to sixth stages. The substrates of the MOS transistors includedin each group are electrically insulated form the substrates of the MOStransistors included in the other group.

Next, the description will hereinbelow be given with respect to asemiconductor booster circuit according to a second embodiment of thepresent invention with reference to FIGS. 7 and 8.

FIG. 7 is a circuit diagram showing a configuration of the semiconductorbooster circuit according to the second embodiment of the presentinvention.

In FIG. 7, n elements of P-channel MOS transistors Q₃₀ to Q₃₄ areconnected in cascade to configure a booster circuit having n stages.Substrate portions of the respective transistors Q₃₀ to Q₃₄ areelectrically insulated from one another, and also gate terminals and thesubstrate portions are connected to respective source terminals N₁ toN₃₅. Then, a clock signal φ_(A) or φ_(B) which is shown in FIG. 8 isinputted to the source terminals N₃₀ to N₃₅ through capacitors C₃₀ toC₃₅, respectively.

In the booster circuit of the present embodiment, as an inputted signal,the power supply voltage Vdd is inputted from a source terminal N₃₇ of aP-channel MOS transistor Q₃₆ to a drain terminal N₃₀ of the transistorQ₃₀. As an output signal, an output voltage V_(POUT) is outputted froman output terminal N₃₆ through a P-channel MOS transistor Q₃₅.

The clock signals φ_(A) and φ_(B) are, as shown in FIG. 8, in oppositephase with each other and have the amplitude of a voltage V_(φ).

In addition, the device structure of the transistors Q₃₀ to Q₃₄ of thepresent embodiment may be the same as that shown in FIG. 6. That is, theN type well regions 11 are formed in the P type semiconductor substrate,and in each of the N type well regions 11, the polycrystalline siliconlayer 16 which is formed on the substrate portion of the well region 11with an intermediate gate oxide film 15 therebetween is provided as thegate electrode, and also the P⁺ type impurity diffusion layer 12 isprovided as the source/drain region. In such a manner, the MOStransistor is formed.

The P⁺ type impurity diffusion layer 12 of the source side of each ofthe transistors is connected to the N type well region 11 through the N⁺type impurity diffusion layer 14, and also the source of the transistorin the preceding stage is connected to the drain of the transistor inthe subsequent stage. As a result, the potential at the N type wellregion as the substrate portion of each of the transistors is fixed tothe source potential of each of the transistors, and hence the substrateeffect is effectively prevented from occurring.

In addition, the PN junction, which is formed between the P⁺ typeimpurity diffusion layer 12 of the drain side and the N type well regionof each of the transistors, is biased in the forward direction, wherebythrough that PN junction, the electric charges are transferred from thenode N_(A) to the node N_(B) and from the node N_(B) to the node N_(D)through the N type well region 11 of the substrate portion and the N⁺type impurity diffusion layer 14. In the case of the present embodiment,each transistor is not rendered substantially perfectly conductiveunlike the state as shown in FIGS. 5B and 5E of the above-mentionedfirst embodiment, and hence the transfer of the electric charges fromthe preceding stage to the subsequent stage is performed through theabove-mentioned PN junction. Therefore, in the case of the presentembodiment, the potential difference corresponding to the forward biasvoltage V_(F) (normally, about 0.7V) across the PN junction which isindependent of the threshold voltage Vt of the MOS transistor isutilized for the boosting operation, and also V_(F) is employed insteadof Vt in the above-mentioned expressions (1) and (2). Since the forwardbias voltage V_(F) across the PN junction is not influenced by thesubstrate effect at all, it is possible to realize the booster circuitin which even when the number of stages of the booster circuit isincreased, the reduction of the boosting capability due to the substrateeffect does not occur at all.

More specifically, in the present embodiment, as shown in FIG. 7, thesubstrate portions of the transistors Q₃₀ to Q₃₄ are electricallyconnected to the source terminals N₃₁ to N₃₅, respectively, whereby thePN junction which is formed in the boundary between the drain and thesubstrate portion is connected in parallel between the source and thedrain of each of the transistors Q₃₀ to Q₃₄. Then, when transferring theelectric charges from the preceding stage to the subsequent stage in thebooster circuit, the PN junction is rendered conductive, whereby thepotential at the substrate portion of each of the transistors Q₃₀ to Q₃₄can be fixed to the potential difference corresponding to the forwardbias voltage V_(F) (normally, about 0.7V) across the PN junction.Therefore, it is possible to suppress the influence of the substrateeffect.

Next, the description will hereinbelow be given with respect to asemiconductor booster circuit according to a third embodiment of thepresent invention with reference to FIGS. 9 and 10.

FIG. 9 is a circuit diagram showing a configuration of the semiconductorbooster circuit according to the third embodiment of the presentinvention.

In FIG. 9, n N-channel MOS transistors Q₄₀ to Q₄₄ are connected incascade to configure the booster circuit having n stages. Substrateportions of the respective transistors Q₄₀ to Q₄₄ are electricallyinsulated from one another, and also the substrate portions and gateterminals are connected to respective source terminals N₄₀ to N₄₄. Then,the clock signal φ_(A) or φ_(B) which is the same as that shown in FIG.8 is inputted to the terminals N₄₀ to N₄₄ through capacitors C₄₀ to C₄₄,respectively.

In the booster circuit according to the present embodiment, the powersupply voltage Vdd is inputted as an input signal from a source terminalN₄₇ of an N-channel MOS transistor Q₄₅ to the terminal N₄₀, and also theoutput voltage V_(POUT) is outputted as an output signal from an outputterminal N₄₆ through the N-channel MOS transistor Q₄₄.

FIG. 10 shows a device structure of the transistors Q₄₀ to Q₄₄ accordingto the present embodiment.

In FIG. 10, P type well regions 51 are formed in an N type semiconductorsubstrate 50, and in each of the P type well regions 51, apolycrystalline silicon layer 56 which is formed on the substrateportion of the well region 11 with a gate oxide film 55 disposedtherebetween is provided as a gate electrode, and also an N⁺ typeimpurity diffusion layer 52 is provided as a source/drain region. Insuch a manner, the MOS transistor is formed.

The N⁺ type impurity diffusion layer 52 of the source side of each ofthe transistors is electrically connected to the P type well region 51,in which the transistor is formed, through the P⁺ type impuritydiffusion layer 54, and the source of the transistor in the precedingstage is connected to the drain of the transistor in the subsequentstage.

As a result, the potential at the P type well region of the substrateportion of each of the transistors is fixed to the source potential ofeach of the transistors, and hence the substrate effect can beeffectively prevented from occurring.

In addition, the PN junction is formed between the N⁺ impurity diffusionlayer 52 of the drain side and the P type well region 51 of each of thetransistors. When in the operation, the PN junction is biased in theforward direction, the potential at the substrate portion of each of thetransistors is fixed to the forward bias voltage across the PN junction.In such a manner, the substrate effect can be effectively prevented fromoccurring.

As described above, in the semiconductor booster circuit according tothe third embodiment of the present invention, the substrate portions ofthe MOS transistors are electrically insulated from one another, andalso the substrate portions are electrically connected to the sourceterminals of the MOS transistors, respectively, whereby it is possibleto prevent the increase of the threshold voltage Vt due to the substrateeffect. Therefore, it is possible to obtain the output voltage V_(POUT)proportional to the number n of stages of the semiconductor boostercircuit.

In addition, with respect to the device structure, as shown in FIG. 10,the P type well regions 51 in which the transistors Q₄₀ to Q₄₄ arerespectively formed are formed independently of each other and also theP⁺ type impurity diffusion region of each of the P type well regions iselectrically connected to the N⁺ type impurity diffusion region 52 ofthe source side of each of the transistors Q₄₀ to Q₄₄. Therefore, inparticular, the number of manufacturing processes is not increased atall.

In addition, the substrate portions of the transistors Q₄₀ to Q₄₄ areelectrically connected to the source terminals N₄₀ to N₄₄, respectively,whereby the PN junction which is formed in the boundary between thedrain and the substrate portion is connected in parallel between thesource and the drain of each of the transistors Q₄₀ to Q₄₄. Then, whentransferring the electric charges from the preceding stage to thesubsequent stage in the booster circuit, the PN junction is switched tothe on state, whereby the potential at the substrate portion of each ofthe transistors Q₄₀ to Q₄₄ can be fixed to the potential differencecorresponding to the forward bias voltage V_(F) (normally, about 0.7V)across the PN junction. Thus, it is possible to suppress the influenceof the substrate effect.

In the semiconductor booster circuits according to the second and thirdembodiments of the present invention, the forward junction bias voltageV_(F) can be employed instead of the threshold voltage Vt in theabove-mentioned expressions (1) and (2). In particular, in the casewhere the threshold voltage Vt is larger than the forward junction biasvoltage V_(F), since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage in the boostercircuit is reduced, it is possible to improve the boosting capability ofthe booster circuit. That is, the voltage drop when the electric chargesare transferred to the subsequent stage depends on the smaller one ofthe threshold voltage Vt and the forward junction bias voltage V_(F).

For example, in the case where the power supply voltage Vdd is 2.5V andthe number n of stages of the booster circuit is 20, assuming that thecapacitance ratio C/(C+Cs) is 0.9, the absolute value of the thresholdvoltage |Vt| is 0.6V, the load current I_(OUT) in the output stage is0A, and the forward junction bias voltage V_(F) across the PN junctionis 0.7V, only 20V can be obtained as the output voltage V_(POUT) in theconventional booster circuit. But in the booster circuit according tothe third embodiment of the present invention, about 33V can be obtainedas the output voltage V_(POUT).

In addition, for example, in the case where the power supply voltage Vddis 2.0V, assuming that the capacitance ratio C/(C+Cs) is 0.9, theabsolute value of the threshold voltage |Vt| is 0.6V, the load currentI_(OUT) in the output stage is 0A, and the forward junction bias voltageV_(F) across the PN junction is 0.7V, only 12V can be obtained as theoutput voltage V_(POUT) in the convention booster circuit, even when thenumber n of stages of the booster circuit is 50. But in the boostercircuit according to the third embodiment of the present invention, whenthe number n of stages of the booster circuit is 20, about 23V can beobtained as the output voltage V_(POUT), and also when the number n ofstages of the booster circuit is 50, about 56V can be obtained.

In the semiconductor booster circuits according to the second and thirdembodiments of the present invention, assuming that the forward junctionbias voltage V_(F) across the PN junction is 0.7V, and the capacitanceratio C/(C+Cs) is 0.9, the lower limit of the boostable power supplyvoltage Vdd is about 0.8V.

In the above, the description has been given with respect to the first,second and third embodiments of the present invention since in thebooster circuit according to the first embodiment, the voltage drop whentransferring the electric charges to the subsequent stage can be madesubstantially zero, and hence, the booster circuit according to thefirst embodiment has the larger boosting capability as compared with thebooster circuits according to the second and third embodiments. Inparticular, in the power supply voltage Vdd of about 0.8V to 2.0V, thedifference in the boosting capability between the booster circuitaccording to the first embodiment and the booster circuit according tothe second or third embodiment becomes remarkable large.

In particular, in the power supply voltage Vdd of about 0.8V to 2.0V,when the desired output voltage is larger, the number n of stages needsto be increased in the booster circuits according to the second andthird embodiments due to the voltage drop when transferring the electriccharges to the subsequent stage. However, in the booster circuitaccording to the first embodiment, this is not required. For example, inthe case where the power supply voltage Vdd is 2.0V, the number n ofstages of the booster circuit required for obtaining 23V as the outputvoltage V_(POUT) is 20 in the booster circuits according to the secondand third embodiments, but only 12 in the booster circuit according tothe first embodiment.

On the other hand, the booster circuit according to the second or thirdembodiment is advantageous as compared with the booster circuitaccording to the first embodiment in that the circuit configuration issimpler and also only two kinds of clock signals are sufficient.

In any one of the above-mentioned embodiments, since the substrateportions of the MOS transistors are electrically insulated from oneanother, and also the substrate portions are electrically connected tothe source terminals of the MOS transistors, respectively, the substrateeffect can be effectively prevented from occurring. Therefore, the highboosting capability can be obtained.

In addition, no complicated manufacturing process is especiallyrequired.

Further, in the case where the same boosting capability is obtained, thenumber of stages of the booster circuit can be further reduced ascompared with the prior art.

Therefore, in the above-mentioned expression (1), the threshold voltageVt can be regarded as zero, and therefore, as compared with theconventional booster circuit, the boosting operation can be moreefficiently performed. Thus, even in the case where the number n ofstages of the booster circuit, and the power supply voltage Vdd are theas those of the conventional booster circuit, it is possible to obtain alarger output voltage V_(POUT) than that of the conventional boostercircuit.

For example, in the case where the power supply voltage Vdd is 2.5V, andthe number n of stages of the booster circuit is 20, assuming that thecapacitance ratio C/(C+Cs) is 0.9, the absolute value of the thresholdvoltage |Vt| is 0.6V, the load current I_(OUT) in the output stage iszero, and the boosted voltage Vhh is 3.0V, only 20V can be obtained asthe output voltage V_(POUT) in the conventional circuit, but in thebooster circuit according to the present embodiment, about 47V can beobtained as the output voltage V_(POUT).

This means that in the case where the output voltage V_(POUT) is thesame, the booster circuit according to the present embodiment canprovide a larger load current I_(OUT) than that in the conventionalcircuit.

In addition, in the booster circuit according to the present embodiment,as can be seen from FIG. 14, even with a low power supply voltage Vddwhich can not be boosted by the conventional circuit, the desired outputvoltage can be obtained.

For example, assuming that the capacitance ratio C/(C+Cs) is 0.9, theabsolute value of the threshold voltage |Vt| is 0.6V, the load currentI_(OUT) in the output stage is zero, and the boosted voltage Vhh is3.0V, the power supply voltage Vdd needs to be set to 2.5V or more, inthe conventional booster circuit, in order to obtain 20V as the outputvoltage V_(POUT), but only 1.5V is sufficient for the power supplyvoltage Vdd in the booster circuit according to the present embodiment.

According to the fourth embodiment, since the clock signal which is usedto render the MOS transistor constituting each of the stages conductiveis boosted so as to have a larger amplitude than the power supplyvoltage Vdd, the desired output voltage can be obtained even in the casewhere the power supply voltage is low.

In addition, in the case where the power supply voltage is constant, alarger load current than that in the prior art can be obtained.

Furthermore, in the case where the same output voltage as that in theprior art is to be obtained, the number of stages of the booster circuitcan be further reduced as compared with the prior art.

Next, the description will hereinbelow be given with respect to a fifthembodiment of the present invention with reference to FIGS. 11 and 12.

A circuit configuration shown in FIG. 11 is identical to that of FIG. 1except for the provision of bootstrap circuits BS₇₁ and BS₇₂ illustratedin the lower half of the figure. Therefore, the operation of the boostercircuit according to the fifth embodiment of the present invention issubstantially the same as that of the booster circuit according to thefirst embodiment. That is, the configuration of the first and secondstages which are consecutive in the booster circuit of the fifthembodiment is the same as that of FIG. 2. Then, when the clock signalsφ_(1A), φ_(1B), φ_(2A) and φ_(2B) are inputted according to the timingdiagram as shown in FIG. 12 in the booster circuit if FIG. 11, the statein charge of the operation of each of the transistors of the boostercircuit as shown in FIG. 2 and the tendency in change of the potentialsat the nodes N_(A), N_(B), N_(C) and N_(D) are the same as those in thefirst embodiment shown in FIGS. 5A to 5F and FIGS. 4A and 4D. The onlydifferences between the first embodiment and the fifth embodiment are asfollows.

Then, when the clock signals φ_(1A), φ_(1B), φ_(2A) and φ_(2B) areinputted according to the timing diagram as shown in FIG. 16 in thebooster circuit of FIG. 15, the state in change of the operation of eachof the transistors of the booster circuit as shown in FIG. 2 and thetendency in change of the potentials at the nodes N_(A), N_(B), N_(C)and N_(D) are the same as those in the first embodiment shown in FIGS.5A to 5F and FIGS. 4A and 4D. The only differences between the firstembodiment and the fifth embodiment are as follows.

(a) For a period of time of (II) of FIG. 12, the potential at the gateterminal N_(C) of the transistor M₁ is dropped as shown in FIG. 4C.However, the voltage drop is equal to the power supply voltage Vdd inthe first embodiment, but is equal to the boosted voltage Vhh in thefifth embodiment.

(b) For a period of time of (III) of FIG. 12, the potential at the gateterminal N_(C) of the transistor M₁ is raised as shown in FIG. 4C. Inthis connection, the raised voltage is equal to the power supply voltageVdd in the first embodiment, but is equal to the boosted voltage Vhh inthe fifth embodiment.

(c) For a period of time of (V) of FIG. 12, the potential at the gateterminal N_(E) of the transistor M₃ is dropped. In this connection, thevoltage drop is equal to the power supply voltage Vdd in the firstembodiment, but is equal to the boosted voltage Vhh in the fifthembodiment.

(d) For a period of time of (VI) of FIG. 12, the potential at the gateterminal N_(E) of the transistor M₃ is raised. In this connection, theraised voltage is equal to the power supply voltage Vdd in the firstembodiment, but is equal to the boosted voltage Vhh in the fifthembodiment.

Next, the description will hereinbelow be given with respect to theoperation of the bootstrap circuit BS₇₁ with reference to FIGS. 11 and12.

Firstly, the level of the clock signal CLK₂ is shown in FIG. 13 ischanged from 0V up to Vdd. At first, the potential of φ_(2A) is changedfrom 0V to Vdd−Vt (Vt is the threshold voltage of the transistor Q₈₄).The threshold voltage Vt of the transistor Q₈₄ is, for example, 0.1V.When Vdd=1V, and the clock signal CLK₂ is changed from 0V to 1V, theinitial potential of φ_(2A) becomes 0.7V (Vt of the transistor Q₈₄ israised by about 0.2V due to the back bias effect). At the same time, theinverter IV₈₅ performs the inversion operation at the time when thelevel of the input voltage φ_(2A) has exceeded the logical thresholdvoltage (normally, about Vdd/2, and also the potential at the node N₉₀is dropped from Vdd to 0V. As a result, the transistor Q₈₅ is turned on.

Next, on the basis of the function of both the inverter IV₈₄ and thecapacitor C₈₃, the potential at the node N₈₇ is changed from Vdd down to0V after a

predetermined time delay from the clock signal CLK₂ and the node N₉₀.Therefore, although the transistor Q₈₆ is initially in the on-state,after a

predetermined time delay, the transistor Q₈₆ is turned off. Until alapse of the predetermined time delay, both the transistors Q₈₅ and Q₈₆are in the on state. In this connection, by setting the on-resistance ofthe transistor Q₈₆ to a value sufficiently smaller than theon-resistance of the transistor Q₈₅, the potential at the node N₈₈ ismaintained at about 0V until a lapse of the predetermined time delay.That is, after a lapse of the predetermined delay time, the potential atthe node N₈₈ is changed from about 0V to Vdd.

Next, at the same time the potential at the node N₈₈ is changed fromabout 0V to Vdd, the potential of the clock signal φ_(2A) goes to(2Vdd−Vt) on the basis of the function of the capacitor C₈₂. Thus, it ispossible to obtain the larger voltage than Vdd. For example, in the caseof Vdd=1V, the level of the clock signal φ_(2A) settles to 1.7V.

The above description also applies to the other bootstrap circuit BS₇₂.

Therefore, by inputting the clock signals CLK₂ and CLK₃ to the bootstrapcircuits BS₇₁ and BS₇₃, respectively, it is possible to obtain the clocksignals φ_(2A) and φ_(2B) each having a larger amplitude than the powersupply voltage Vdd.

The fifth embodiment offers basically the same effects as those of thefirst embodiment in that the high output voltage can be obtained. Inaddition, in the fifth embodiment, the level of each of the clocksignals φ_(2A) and φ_(2B) is boosted by the bootstrap circuit BS₇₁ orBS₇₂ to a larger amplitude than the power supply voltage Vdd, wherebythe gate voltage of each of the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . ,Q₉, which are connected in cascade, can be made higher than that in theprior art. Therefore, even if the threshold voltage Vt is increased dueto the substrate effect, the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉can be normally turned on, and hence it is possible to obtain the outputvoltage V_(POUT) which is increased in proportion to the number n ofstages of the semiconductor booster circuit.

In addition, in the semiconductor booster circuit according to thepresent embodiment, the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉ aredriven by the clock signals φ_(2A) and φ_(2B) which are respectivelyobtained by boosting the clock signals CLK₂ and CLK₃ to a largeramplitude than the power supply voltage Vdd, whereby the MOS transistorsQ₁, Q₃, Q₅, Q₇, . . . , Q₉ can be sufficiently turned on even with thevery low power supply voltage value (e.g., Vdd=0.7 to 1.0V).

In the present embodiment, the lowest power supply voltage which can beboosted is determined by the threshold voltage Vt of each of theP-channel MOS transistors, Q₁, Q₃, Q₅, Q₇, . . . , Q₉ constituting thebooster circuit. As in the first embodiment, in the case where theamplitude V_(φ2) of each of the clock signals φ_(2A) and φ_(2B) is equalto the power supply voltage Vdd, the voltage drop at the node N_(C) in aperiod of time of (II) shown in FIG. 4C does not reach the thresholdvoltage Vt (e.g., −0.6V) of each of the P-channel MOS transistors Q₁,Q₃, Q₅, Q₇, . . . , Q₉ if Vdd becomes

equal to or lower than 1V and hence the P-channel MOS transistors Q₁,Q₃, Q₅, Q₇, . . . , Q₉ can not be sufficiently turned on. On the otherhand, as in the fifth embodiment, the amplitude V_(φ2) of each of theclock signals φ_(2A) and φ_(2B) is boosted by the bootstrap circuit BS₁or BS₂ to a larger amplitude than the power supply voltage Vdd, wherebythe boosting operation can be stably performed even in the very lowpower supply voltage value of Vdd=0.7 to 1.0V. In addition, since theP-channel MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉ can be sufficientlyturned on, it is also possible to prevent the reduction of the boostingcapability of the booster circuit.

Next, the description will hereinbelow be given with respect to a sixthembodiment of the present invention with reference to FIGS. 13 and 14.

FIG. 13 shows a configuration of a semiconductor booster circuitaccording to the sixth embodiment of the present invention.

As shown if FIG. 13, N-channel depletion type MOS transistors M₁₀₁ toM₁₀₈ are connected in series between an input terminal N₁₂₀ and anoutput terminal to configure a booster circuit having four stages. Thatis, each pair of the transistors M₁₀₁ and M₁₀₂; M₁₀₃ and M₁₀₄; M₁₀₅ andM₁₀₆; M₁₀₇ and M₁₀₈ constitute respective stages. Gate terminals of thetransistors M₁₀₁ to M₁₀₈ are respectively connected to drain terminals(represented by nodes N₁₀₀ to N₁₀₇). Then, a clock signal φ_(A) which isshown in FIG. 16 is inputted through capacitors C₁₀₁, C₁₀₃, C₁₀₅ andC₁₀₇, respectively, to the drain terminals N₁₀₀, N₁₀₂, N₁₀₄ and N₁₀₆ andalso a clock signal φ_(B) which is in opposite phase with the clocksignal φ_(A) is inputted through capacitors C₁₀₂, C₁₀₄, C₁₀₆ and C₁₀₈,respectively, to the drain terminals N₁₀₁, N₁₀₃, N₁₀₅ and N₁₀₇. Inaddition, both drain terminals and gate terminals of N-channel MOStransistors M₁₀₂ and M₁₂₁ are connected to the input terminal(represented by a node N₁₂₀), and substrate terminals thereof areconnected to a ground terminal (represented by a node N₁₂₁).

In addition, substrate terminals of the transistors M₁₀₁ to M₁₀₈ aredivided into two groups, as will be described later, i.e., the group ofthe transistors M₁₀₁ to M₁₀₄ and the group of the transistors M₁₀₅ toM₁₀₈. In this connection, the substrate terminals of the transistorsM₁₀₁ to M₁₀₄ and the substrate terminals of the transistors M₁₀₅ to M₁₀₈are respectively connected to the drain terminal N₁₀₀ of the transistorM₁₀₁ and the drain terminal N₁₀₄ of the transistor M₁₀₅.

That is, the node N₁₀₀ is connected to the source terminal of thetransistor M₁₂₀, both the drain terminal and the gate terminal of thetransistor M₁₀₁, one terminal of the capacitor C₁₀₁ and the substrateterminals of the transistors M₁₀₁ to M₁₀₄. The node N₁₀₁ is connected tothe source terminal of the transistor M₁₂₁, both the drain terminal andthe gate terminal of the transistor M₁₀₂, the source terminal of thetransistor M₁₀₁ and one terminal of the capacitor C₁₀₂. The node N₁₀₂ isconnected to both the drain terminal and the gate terminal of thetransistor M₁₀₃, the source terminal of the transistor M₁₀₂ and oneterminal of the capacitor C₁₀₃. The node N₁₀₃ is connected to both thedrain terminal and the gate terminal of the transistor M₁₀₄, the sourceterminal of the transistor M₁₀₃ and one terminal of the capacitor C₁₀₄.The node N₁₀₄ is connected to both the drain terminal and the gateterminal of the transistor M₁₀₅, the source terminal of the transistorM₁₀₄, one terminal of the capacitor C₁₀₅ and the substrate terminals ofthe transistors M₁₀₅ to M₁₀₈. The node N₁₀₅ is connected to both thedrain terminal and the gate terminal of the transistor M₁₀₆, the sourceterminal of the transistor M₁₀₅ and one terminal of the capacitor C₁₀₆.The node N₁₀₆ is connected to both the drain terminal and the gateterminal of the transistor M₁₀₇, the source terminal of the transistorM₁₀₆ and one terminal of the capacitor C₁₀₇. In addition, the node N₁₀₇is connected to both the drain terminal and the gate terminal of thetransistor M₁₀₈, the source terminal of the transistor M₁₀₇ and oneterminal of the capacitor C₁₀₈. Further, the output terminal of thesemiconductor booster circuit is connected to the source terminal of thetransistor M₁₀₈.

In this configuration, the series-connected four stages are divided intoa group of two stages of the input side including the transistors M₁₀₁to M₁₀₄ and a group of two stages of the output side including thetransistors M₁₀₅ to M₁₀₈. Therefore, the substrate terminals of thetransistors M₁₀₁ to M₁₀₈ are divided into the group of substrateterminals of the transistors M₁₀₁ to M₁₀₄ and the group of substrateterminals of the transistors M₁₀₅ to M₁₀₈. In this connection, thesubstrate terminals of the transistors M₁₀₁ to M₁₀₄ are connected to thedrain terminal N₁₀₀ of the transistor M₁₀₁ and the substrate terminalsof the transistors M₁₀₅ to M₁₀₈ are connected to the drain terminal N₁₀₄of the transistor M₁₀₅. Therefore, as compared with the conventionalbooster circuit shown in FIG. 22, a substrate bias voltage Vbs of thetransistors M₁₀₁ to M₁₀₇ in the booster circuit of the presentembodiment is smaller than that of the transistors M₁ to M₇ in theconventional booster circuit. As a result, the threshold voltage Vt ofthe transistors M₁₀₅ to M₁₀₈ in the booster circuit of the presentembodiment is lower than that of the transistors M₅ to M₈ in theconventional booster circuit. As a result, as compared with theconventional booster circuit, the boosting capability is furtherimproved in the booster circuit of the present embodiment so that thehigh output voltage is obtained, and also the number of stages requiredfor obtaining the same output voltage can be further reduced, ascompared with the conventional booster circuit. In addition, since thethreshold voltage Vt in each of the stages is lowered, the lower limitof the boostable power supply voltage Vdd becomes small, and hence thedrive with the low power supply voltage becomes possible.

Next, the description will hereinbelow be given with respect to thedevice structure of the booster circuit shown in FIG. 13 with referenceto FIG. 14.

As shown in FIG. 14, in an N type well region 402 which is formed in a Ptype semiconductor substrate 401, P type well regions 403, 404 and 405are respectively formed. P⁺ type impurity diffusion layer 406 and N⁺type impurity diffusion layers 409 and 410 are respectively formed inthe P⁺ type well region 403, and also a polycrystalline silicon film 421as a gate electrode is formed above a channel region between the N typeimpurity diffusion layers 409 and 410 as the drain and the source withan interposed gate oxide film (not shown), thereby constituting thetransistor M₁₂₀. In addition, a P⁺ type impurity diffusion layer 407 andN⁺ type impurity diffusion layers 411 to 415 are respectively formed inthe P type well region 404, and also polycrystalline silicon films 422to 425 as gate electrodes of the transistors are formed above channelregions between N⁺ type impurity diffusion layers 411 to 415constituting the drains or the sources of the transistors with anintermediate gate oxide film (not shown), thereby constituting the fourtransistors M₁₀₁ to M₁₀₄. In addition, a P⁺ type impurity diffusionlayer 408 and N⁺ type impurity diffusion layers 416 to 420 constitutingthe drains or the sources of the transistors with ah intermediate gateoxide film (not shown), thereby constituting the four transistors M₁₀₅to M₁₀₈.

The polycrystalline silicon films 422 to 425 as the gate electrodes ofthe transistors M₁₀₁ to M₁₀₄ are respectively connected to the N⁺ typeimpurity diffusion layers 411 to 414, and the polycrystalline siliconfilms 426 to 429 as the gate electrodes of the transistors M₁₀₅ to M₁₀₈are respectively connected to the N⁺ type impurity diffusion layers 416to 419. In addition, the clock signal φ_(A) as shown in FIG. 4 isinputted through the capacitors C₁₀₁, C₁₀₃, C₁₀₅ and C₁₀₇, respectively,to the polycrystalline silicon films 422, 424, 426 and 428 as the gateelectrodes of the transistors M₁₀₁, M₁₀₃, M₁₀₅ and M₁₀₇ and the clocksignal φ_(B) which is in opposite phase with the clock signal φ_(A) isinputted through the capacitors C₁₀₂, C₁₀₄, C₁₀₆ and C₁₀₈, respectivelyto the polycrystalline silicon films 423, 425, 427 and 429 as the gateelectrodes of the transistors M₁₀₂, M₁₀₄, M₁₀₆ and M₁₀₈. In addition,both the N⁺ type impurity diffusion layer 409 as the drain and thepolycrystalline silicon film 421 as the gate electrode of the transistorM₁₂₀ are connected to the power supply terminal N₁₂₀. The P type wellregion 403 is connected to the ground terminal N₁₂₁ through the P⁺ typeimpurity diffusion layer 406, and hence the substrate potential of thetransistor M₁₂₀ is equal to the potential at the P type well region 403.In addition, the P type well region 404 is connected to both the N⁺ typeimpurity diffusion layer 410 as the source of the transistor M₁₂₀ andthe N⁺ type impurity diffusion layer 411 as the drain of the transistorM₁₀₁ through the P⁺ type impurity diffusion layer 407, and hence thesubstrate potential of each of the transistors M₁₀₁ to M₁₀₄ is equal tothe potential at the P type well region 404. Further, the P type wellregion 405 is connected to both the N⁺ type impurity diffusion layer 415as the source of the transistor M₁₀₄ and the N⁺ type impurity diffusionlayer 416 as the drain of the transistor M₁₀₅ through the P⁺ typeimpurity diffusion layer 408, and hence the substrate potential of eachof the transistors M₁₀₅ to M₁₀₈ is equal to the potential at the P typewell region 405.

Although in the embodiment described above, the substrate portions ofthe eight transistors M₁₀₁ to M₁₀₈ constituting the booster circuit aredivided into two groups, the number of groups is not limited thereto.For example, the substrate portions are divided by every stage, and thusthe four groups may be formed. But, if each division is too small,although the boosting efficiency is improved, there arises a problemthat the integration of the elements can not be increased. Incidentally,although the above-mentioned embodiment has the circuit configurationhaving the four stages, it is to be understood that the number of stagesis not limited thereto.

Next, the description will hereinbelow be given with respect to aseventh embodiment of the present invention with reference to FIGS. 15and 17.

As shown in FIG. 15, four circuit blocks PCE₀₁ to PCE₀₄ are connected incascade to configure the semiconductor booster circuit according to theseventh embodiment of the present invention. Each of the circuit blocksPCE₀₁ to PCE₀₄ is configured by connecting P-channel MOS transistorsP₂₀₁ and P₂₀₂ in series with each other. Now, to a drain terminal N₂₀₁of the transistor P₂₀₁, a clock signal φ_(1A) which is shown in FIG. 17is inputted through a capacitor C₂₀₂. To a drain terminal N₂₀₂ of thetransistor P₂₀₂, a clock signal φ_(1B) is inputted through a capacitorC₂₀₃. In addition, to a gate terminal N₂₀₅ of the transistor P₂₀₂, aclock signal φ_(1B) is inputted through a capacitor C₂₀₃. In addition,to a gate terminal N₂₀₅ of the transistor P₂₀₂ a clock signal φ_(2B) isinputted through a capacitor C₂₀₄. Further, a P-channel MOS transistorP₂₀₃ is connected between the source terminal N₂₀₂ and the gate terminalN₂₀₃ of the transistor P₂₀₁, and the gate terminal of the transistorP₂₀₃ is connected to the drain terminal N₂₀₁ of the transistor P₂₀₁. Inaddition, a P-channel MOS transistor P₂₀₄ is connected between thesource terminal N₂₀₄ and the gate terminal N₂₀₅ of the transistor P₂₀₂,and the gate terminal of the transistor P₂₀₄ is connected to the drainterminal N₂₀₂ of the transistor P₂₀₂.

In addition, drain terminals and gate terminals of N-channel depletiontype MOS transistors M₂₂₀ and M₂₂₁ are respectively connected to a powersupply terminal N₂₂₀, substrate terminals thereof are connected to aground terminal N₂₂₁, and source terminals thereof are respectivelyconnected to the drain terminals N₂₀₁ and N₂₀₂ of the transistors P₂₀₁and P₂₀₂ in the circuit block PCH₀₁. Incidentally, instead of theN-channel depletion type MOS transistors M₂₂₀ and M₂₂₁, N-channelenhancement type MOS transistors may also be used.

Substrate terminals of the four transistors P₂₀₁ to P₂₀₄ in the circuitblocks PCH₀₁ and PCH₀₂ are connected to a substrate terminal SUB₁ formedof a common N type well region, and the substrate terminal SUB₁ isconnected to a source terminal (not shown) of the transistor P₂₀₄ in thecircuit block PCH₀₂. On the other hand, substrate terminals of fourtransistors P₂₀₁ to P₂₀₄ in the circuit blocks PCE₀₃ and PC₀₄ areconnected to a substrate terminals SUB₂ formed of a common N type wellregion, and the substrate terminal SUB₂ is connected to the sourceterminal (not shown) of the transistor P₂₀₄ in the circuit block PC₀₄.Incidentally, the substrate terminals SUB₁ and SUB₂ are electricallyinsulated from each other.

The source terminal N₂₀₄ of the transistor P₂₀₂ in the circuit blockPC₀₁ is connected to the drain terminal N₂₀₁ of the transistor P₂₀₁ inthe circuit block PCE₀₂, the source terminal N₂₀₄ of the transistor P₂₀₂in the circuit block PCH₀₂ is connected to the drain terminal N₂₀₁ ofthe transistor P₂₀₁ in the circuit block PCH₀₃, and the source terminalN₂₀₄ of the transistor P₂₀₂ in the circuit block PCH₀₃ is connected tothe drain terminal N₂₀₁ of the transistor P₂₀₁ in the circuit blockPCH₀₄ so that the four circuit blocks PCH₀₁ to PCH₀₄ are connected incascade. In addition, the source terminal of the transistor P₂₀₂ in thecircuit block PCH₀₄ is connected to an output terminal to provide theoutput voltage V_(POUT).

Next, the description will hereinbelow be given with respect to theoperation of the semiconductor booster circuit according to the seventhembodiment of the present invention. Incidentally, in the followingdescription, it is meant by “smaller than the threshold voltage” thatthe potential at the drain or the source is lower than that at the gate,or the potential at the source or the drain is higher than that at thegate, but the difference therebetween is smaller than the thresholdvoltage. By “larger than the threshold voltage”, it is meant that thepotential at the source or the drain is higher than that at the gate andadditionally the difference therebetween is larger than the thresholdvoltage.

Firstly, for a period of time of (I) of FIG. 17, the level of the clocksignal φ_(1A) is the low potential (“L”), and the level of each of theclock signals φ_(2A), φ_(1B) and φ_(2B) are the high potential (“H”).Thus, a current is caused to flow from the power supply terminal N₂₂₀shown in FIG. 15 to the drain terminal N₂₀₁ of the transistor P₂₀₁through the transistor M₂₂₀, and hence the electric charges areaccumulated in the capacitor C₂₀₁. The potential at the drain terminalN₂₀₂ of the transistor P₂₀₂ is higher than its previous potentialexisting when the level of the clock signal 1B was previously “L” byV_(φ)C/(C+Cs) (V_(φ) is the amplitude of each of the clock signalsφ_(1A) and φ_(1B)) shown in the above-mentioned expression (1). Thus, ifthe relation in magnitude between the potential at the drain terminalN₂₀₁ of the transistor P₂₀₁ and the potential at the drain terminal N₂₀₂of the transistor P₂₀₂ becomes larger than the threshold value of thetransistor P₂₀₃, the transistor P₂₀₃ is turned on, and hence theconduction is established between the gate terminal N₂₀₃ of thetransistor P₂₀₁ and the drain terminal N₂₀₂ of the transistor P₂₀₂. Atthis time, since the potential between the gate terminal N₂₀₃ and thedrain terminal N₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁is lower than the threshold voltage of the transistor P₂₀₁, thetransistor P₂₀₁ is turned off. In addition, both the transistors P₂₀₂and P₂₀₄ are turned off since the potential between the gate terminaland the drain terminal or the source terminal is lower than thethreshold voltage.

Next, when the operation proceeds from a period of time of (I) to aperiod of time of (II), the level of each of the clock signals φ_(2A)and φ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “L” to “H” and the level of the clock signal φ_(1B) ischanged from “H” to “L”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “L” to “H”, and also thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “H” to “L”. Then, at the time point when the potential between thegate terminal N₂₀₁ and the drain terminal N₂₀₂ or the source terminalN₂₀₃ of the transistor P₂₀₃ has become lower than the threshold voltageof the transistor P₂₀₃, the transistor P₂₀₃ is switched from the onstate to the off state. In addition, at the time point when thepotential between the gate terminal N₂₀₂ and the drain terminal N₂₀₄ orthe source terminal N₂₀₅ of the transistor P₂₀₄ has become larger thanthe threshold voltage of the transistor P₂₀₄, the transistor P₂₀₄ isswitched from the off state to the on state, and also the conduction isestablished between the drain terminal N₂₀₄ and the source terminal N₂₀₅of the transistor P₂₀₄.

Next, when the operation proceeds from a period of time of (II) to aperiod of time of (III), the level of each of the clock signals φ_(1A)and φ_(2B) remains “H”, and the level of the clock signal φ_(1B) remains“L”, and also the level of the clock signal φ_(2A) is changed from “H”to “L”. Therefore, the potential at the gate terminal N₂₀₃ of thetransistor P₂₀₁ is changed from “H” to “L”, and hence at the time pointwhen the potential between the gate terminal N₂₀₃ and the drain terminalN₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁ has becomelarger than the threshold voltage of the transistor P₂₀₁, the transistorP₂₀₁ is switched from he off state to the on state, a current is causedto flow from the drain terminal N₂₀₁ of the transistor P₂₀₁ to the drainterminal N₂₀₂ of the transistor P₂₀₂, and the potential at the drainterminal N₂₀₂ of the transistor P₂₀₂ is raised.

Next, when the operation proceeds from a period of time of (III) to aperiod of time of (IV), the level of each of the clock signals φ_(1A)and φ_(2B) remains “H”, and the level of the clock signal φ_(1B) remains“L”, and also the level of the clock signal φ_(2A) is changed from “L”to “E”. Therefore, the potential at the gate terminal N₂₀₃ of thetransistor P₂₀₁ is changed from “L” to “H”, and also the transistor P₂₀₁is switched from the on state to the off state.

Next, when the operation proceeds from a period of time of (IV) to aperiod of time of (V), the level of each of the clock signals φ_(2A) andφ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “H” to “L”, and the level of the clock signal φ_(1B) ischanged from “L” to “H”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “H” to “L”, and thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “L” to “H”, and at the time point when the potential between thegate terminal N₂₀₁ and the drain terminal N₂₀₂ or the source terminalN₂₀₃ of the transistor P₂₀₃ has become larger than the threshold voltageof the transistor P₂₀₃, the transistor P₂₀₃ is switched from the offstate to the on state, and the conduction is established between thedrain terminal N₂₀₂ and the source terminal N₂₀₃ of the transistor P₂₀₃.In addition, at the time point when the potential between the gateterminal N₂₀₂ and the drain terminal N₂₀₄ or the source terminal N₂₀₅ ofthe transistor P₂₀₄ has become smaller than the threshold voltage of thetransistor P₂₀₄, the transistor P₂₀₄ is switched from the on state tothe off state.

Next, when the operation proceeds from a period of time of (V) to aperiod of time of (VI), the level of each of the clock signals φ_(2A)and φ_(1B) remains “H”, the level of the clock signal φ_(1A) remains“L”, and the level of the clock signal φ_(2A) is changed from “H” to“L”. Therefore, the potential at the gate terminal N₂₀₅ of thetransistor P₂₀₂ is changed from “H” to “L”, and hence at the time pointwhen the potential between the gate terminal N₂₀₅ and the drain terminalN₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ has becomelarger than the threshold voltage of the transistor P₂₀₂, the transistorP₂₀₂ is changed from the off state to the on state, a current is causedto flow from the drain terminal N₂₀₂ to the source terminal N₂₀₄ of thetransistor P₂₀₂, and the potential at the source terminal N₂₀₄ of thetransistor P₂₀₂ is raised.

Next, when the operation proceeds from a period of time of (VI) to aperiod of time of (VII), the level of each of the clock signals φ_(2A)and φ_(1B) remains “E”, and also the level of the clock signal φ_(1A)remains “L”, and the level of the clock signal φ_(2B) is changed from“L” to “E”. Therefore, the potential at the gate terminal N₂₀₅ of thetransistor P₂₀₂ is changed from “L” to “E”, and hence at the time pointwhen the potential relation between the gate terminal N₂₀₅ and the drainterminal N₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ hasbecome smaller than the threshold voltage of the transistor P₂₀₂, thetransistor P₂₀₂ is switched from the on state to the off state.

In the above-mentioned operation, with respect to the transistors P₂₀₁and P₂₀₃ and the capacitors C₂₀₁ and C₂₀₂ for example, when thepotential at the node N₂₀₁ is “E” and the potential at each of the nodesN₂₀₂ and N₂₀₃ is “L” (for a period of time of (III)), the transistorP₂₀₁ is turned on, a current is caused to flow from the node N₂₀₁ to thenode N₂₀₂, and the potential at the node N₂₀₂ is further raised ascompared with its potential at the time before the transistor P₂₀₁ isturned on. Subsequently, when the level of the clock signal φ_(1A) goesto “L”, the level of the clock signal φ_(1B) goes “H”, and also thepotential at the node N₂₀₁ goes to “L” and the potential at the nodeN₂₀₂ goes to “H” (for a period of time of (V)), the transistor P₂₀₃ isturned on, and the node N₂₀₂ becomes conductive with the node N₂₀₃.Therefore, the potential difference between the source and the gate ofthe transistor P₂₀₁ becomes zero. At this time, although the potentialat the node N₂₀₁ becomes lower than that at the node N₂₀₂, no current iscaused to flow between the nodes N₂₀₂ and N₂₀₁ since the transistor P₂₀₁is turned off. In addition, the potential at the node N₂₀₂ becomeshigher than the potential existing when the transistor P₂₀₁ is in the onstate by about Vφ·C/(C+Cs) as shown in the expression (1), and thereforethe potential at the node N₂₀₂ becomes higher than the potentialexisting when the “H” state has been obtained.

The above-mentioned operation is also applicable to the circuit blocksPCH₀₂ to PCE₀₄, and hence the output potential of the circuit blocklocated at preceding stages or closer to the output terminal becomeshigher in the positive direction. That is, the semiconductor boostercircuit according to the seventh embodiment is the positive high voltagegenerating circuit employing the P-channel MOS transistors.

Incidentally, in the semiconductor booster circuit according to theseventh embodiment, for example, since the potential at the substrateterminal SUB₁ is higher than the potential at the sources or drains ofthe transistors P₂₀₁ and P₂₀₂, the absolute value of the thresholdvoltage is increased due to the substrate effect, and hence both thetransistors P₂₀₁ and P₂₀₂ are difficult to be turned on, or there is apossibility that the on-current becomes small. However, the wholesubstrate potentials are divided into the two potentials, i.e., thepotential at SUB₁ and the potential at SUB₂, whereby the increase of thethreshold voltage due to the substrate bias effect is reduced. If thesubstrate potentials are divided into four blocks and the potential ofeach block is controlled, the integration becomes poor but the increaseof the threshold voltage due to the substrate bias effect can be furtherreduced.

In the semiconductor booster circuit according to the seventhembodiment, since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage can be madesubstantially zero, the larger boosting capability is obtained ascompared with the sixth embodiment. In particular, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the difference inboosting capability between the sixth embodiment and the seventhembodiment becomes remarkably large. For example, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the number n of stagesof the booster circuit required for obtaining a desired output voltageneeds to be greatly increased in the booster circuit of the sixthembodiment due to the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage, but in thebooster circuit of the seventh embodiment, it is not required at all.For example, in the case where the power supply voltage Vdd is 2.0V, inthe sixth embodiment, the number of stages of the booster circuitrequired for obtaining the output voltage V_(POUT) of 23V is 20 whereasin the booster circuit of the seventh embodiment, the required number ofstages is only 12.

On the other hand, the booster circuit of the sixth embodiment isadvantageous as compared with the booster circuit of the seventhembodiment in that the configuration is simpler and also only two kindsof clock signals are required.

Incidentally, it is to be understood that in the above-mentionedembodiments, the various changes may be made. For example, the number ofstages of the booster circuit is not limited to four in theabove-mentioned embodiment, and hence it may be set to any valuedetermined in accordance with the voltage to be boosted, the circuitscale and the like. In addition, the N-channel depletion type MOStransistors M₁₀₁ to M₁₀₈ are exemplarily employed as the transistorsconstituting the booster circuit in the sixth embodiment and also theP-channel MOS transistors P₂₀₁ to P₂₀₄ are exemplarily employed as thetransistors constituting the booster circuit in the seventh embodiment.However, as for those transistors, other transistors such as N-channelenhancement type MOS transistors may also be employed. For example, theN-channel MOS transistors M₁₀₁ to M₁₀₈ in the sixth embodiment may besubstituted by P-channel MOS transistors which are formed in the N typewell region, and also the power supply terminal N₁₂₀ may be grounded toprovide the negative high voltage generating circuit. In addition, theP-channel MOS transistors P₂₀₁ to P₂₀₄ in the seventh embodiment may besubstituted by N-channel MOS transistors which are formed in the P typewell region to provide the negative high voltage generating circuit.

In the sixth and seventh embodiments, the substrate terminals of the MOStransistors constituting the booster circuit are divided into thenecessary groups, and also are controlled to the different potentialsfor the groups, whereby it is possible to prevent the substrate biaseffect from occurring. Therefore, the high boosting capability can beobtained and also the increase of the circuit area can be kept to aminimum. Incidentally, the substrate terminals SUB₁ and SUB₂ areelectrically insulated from each other.

The source terminal N₂₀₄ of the transistor P₂₀₂ in the circuit blockPCH₀₁ is connected to the drain terminal N₂₀₁ of the transistor P₂₀₁ inthe circuit block PCH₀₂, the source terminal N₂₀₄ of the transistor P₂₀₂in the circuit block PCH₀₂ is connected to the drain terminal N₂₀₁ ofthe transistor P₂₀₁ in the circuit block PCH₀₃, and the source terminalN₂₀₄ of the transistor P₂₀₂ in the circuit block PCH₀₃ is connected tothe drain terminal N₂₀₁ of the transistor P₂₀₁ in the circuit blockPCH₀₄ so that the four circuit blocks PCH₀₁ to PCH₀₄ are connected incascade. In addition, the source terminal of the transistor P₂₀₂ in thecircuit block PCH₀₄ is connected to an output terminal to output theoutput voltage V_(POUT).

Next, the description will hereinbelow be given with respect to theoperation of the semiconductor booster circuit according to the seventhembodiment of the present invention. Incidentally, in the followingdescription, it is meant by “smaller than the threshold voltage” thatthe potential at the drain or the source is lower than that at the gate,or the potential at the source or the drain is higher than that at thegate, but the difference therebetween is smaller than the thresholdvoltage. By “larger than the threshold voltage”, it is meant that thepotential at the source or the drain is higher than that at the gate andadditionally the difference therebetween is larger than the thresholdvoltage.

Firstly, for a period of time of (I) of FIG. 17, the level of the clocksignal φ_(1A) is the low potential (“L”), and the level of each of theclock signals φ_(2A), φ_(1B) and φ_(2B) are the high potential (“H”).Thus, a current is caused to flow from the power supply terminal N₂₂₀shown in FIG. 15 to the drain terminal N₂₀₁ of the transistor P₂₀₁through the transistor M₂₂₀, and hence the electric charges areaccumulated in the capacitor C₂₀₁. The potential at the drain terminalN₂₀₂ of the transistor P₂₀₂ is higher than its previous potentialexisting when the level of the clock signal 1B was previously “L” byV_(φ)C/(C+Cs) (V_(φ)is the amplitude of each of the clock signals φ_(1A)and φ_(1B)) shown in the above-mentioned expression (1). Thus, if therelation in magnitude between the potential at the drain terminal N₂₀₁of the transistor P₂₀₁ and the potential at the drain terminal N₂₀₂ ofthe transistor P₂₀₂ becomes larger than the threshold value of thetransistor P₂₀₃, the transistor P₂₀₃ is turned on, and hence theconduction is established between the gate terminal N₂₀₃ of thetransistor P₂₀₁ and the drain terminal N₂₀₂ of the transistor P₂₀₂. Atthis time, since the potential between the gate terminal N₂₀₃ and thedrain terminal N₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁is lower than the threshold voltage of the transistor P₂₀₁, thetransistor P₂₀₁ is turned off. In addition, both the transistors P₂₀₂and P₂₀₄ are turned off since the potential between the gate terminaland the drain terminal or the source terminal is lower than thethreshold voltage.

Next, when the operation proceeds from a period of time of (I) to aperiod of time of (II), the level of each of the clock signals φ_(2A)and φ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “L” to “H” and the level of the clock signal φ_(1B) ischanged from “H” to “L”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “L” to “H”, and also thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “H” to “L”. Then, at the time point when the potential relationbetween the gate terminal N₂₀₁ and the drain terminal N₂₀₂ or the sourceterminal N₂₀₃ of the transistor P₂₀₃ has become lower than the thresholdvoltage of the transistor P₂₀₃, the transistor P₂₀₃ is switched from theon state to the off state. In addition, at the time point when thepotential relation between the gate terminal N₂₀₂ and the drain terminalN₂₀₄ or the source terminal N₂₀₅ of the transistor P₂₀₄ has becomelarger than the threshold voltage of the transistor P₂₀₄, the transistorP₂₀₄ is switched from the off state to the on state, and also theconduction is established between the drain terminal N₂₀₄ and the sourceterminal N₂₀₅ of the transistor P₂₀₄.

Next, when the operation proceeds from a period of time of (II) to aperiod of time of (III), the level of each of the clock signals φ_(1A)and φ_(2B) remains “H”, and the level of the clock signal φ_(1B) remains“L”, and also the level of the clock signal φ_(2A) is changed from “H”to “L”. Therefore, the potential at the gate terminal N₂₀₃ of thetransistor P₂₀₁ is changed from “H” to “L”, and hence at the time pointwhen the potential relation between the gate terminal N₂₀₃ and the drainterminal N₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁ hasbecome larger than the threshold voltage of the transistor P₂₀₁, thetransistor P₂₀₁ is switched from the off state to the on state, acurrent is caused to flow from the drain terminal N₂₀₁ of the transistorP₂₀₁ to the drain terminal N₂₀₂ of the transistor P₂₀₂, and thepotential at the drain terminal N₂₀₂ of the transistor P₂₀₂ is raised.

Next, when the operation proceeds from a period of time of (III) to aperiod of time of (IV), the level of each of the clock signals φ_(1A)and φ_(2B) remains “H”, and the level of the clock signal φ_(1B) remains“L”, and also the level of the clock signal φ_(2A) is changed from “L”to “H”. Therefore, the potential at the gate terminal N₂₀₃ of thetransistor P₂₀₁ is changed from “L” to “H”, and also the transistor P₂₀₁is switched from the on state to the off state.

Next, when the operation proceeds from a period of time of (IV) to aperiod of time of (V), the level of each of the clock signals φ_(2A) andφ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “H” to “L”, and the level of the clock signal φ_(1B) ischanged from “L” to “H”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “H” to “L”, and thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “L” to “H”, and at the time point when the potential relationbetween the gate terminal N₂₀₁ and the drain terminal N₂₀₂ or the sourceterminal N₂₀₃ of the transistor P₂₀₃ has become larger than thethreshold voltage of the transistor P₂₀₃, the transistor P₂₀₃ isswitched from the off state to the on state, and the conduction isestablished between the drain terminal N₂₀₂ and the source terminal N₂₀₃of the transistor P₂₀₃. In addition, at the time point when thepotential relation between the gate terminal N₂₀₂ and the drain terminalN₂₀₄ or the source terminal N₂₀₅ of the transistor P₂₀₄ has becomesmaller than the threshold voltage of the transistor P₂₀₄, thetransistor P₂₀₄ is switched from the on state to the off state.

Next, when the operation proceeds from a period of time of (V) to aperiod of time of (VI), the level of each of the clock signals φ2A andφ_(1B) remains “H”, the level of the clock signal φ_(1A) remains “L”,and the level of the clock signal φ_(2A) is changed from “H” to “L”.Therefore, the potential at the gate terminal N₂₀₅ of the transistorP₂₀₂ is changed from “H” to “L”, and hence at the time point when thepotential relation between the gate terminal N₂₀₅ and the drain terminalN₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ has becomelarger than the threshold voltage of the transistor P₂₀₂, the transistorP₂₀₂ is changed from the off state to the on state, a current is causedto flow from the drain terminal N₂₀₂ to the source terminal N₂₀₄ of thetransistor P₂₀₂, and the potential at the source terminal N₂₀₄ of thetransistor P₂₀₂ is raised.

Next, when the operation proceeds from a period of time of (VI) to aperiod of time of (VII), the level of each of the clock signals φ_(2A)and φ_(1B) remains “H”, and also the level of the clock signal φ_(1A)remains “L”, and the level of the clock signal φ_(2B) is changed from“L” to “H”. Therefore, the potential at the gate terminal N₂₀₅ of thetransistor P₂₀₂ is changed from “L” to “H”, and hence at the time pointwhen the potential relation between the gate terminal N₂₀₅ and the drainterminal N₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ hasbecome smaller than the threshold voltage of the transistor P₂₀₂, thetransistor P₂₀₂ is switched from the on state to the off state.

In the above-mentioned operation, with respect to the transistors P₂₀₁and P₂₀₃ and the capacitors C₂₀₁ and C₂₀₂ for example, when thepotential at the node N₂₀₁ is “H” and the potential at each of the nodesN₂₀₂ and N₂₀₃ is “L” (for a period of time of (III)), the transistorP₂₀₁ is turned on, a current is caused to flow from the node N₂₀₁ to thenode N₂₀₂, and hence the potential at the node N₂₀₂ is further raised ascompared with its potential at the time before the transistor P₂₀₁ isturned on. Subsequently, when the level of the clock signal φ_(1A) goesto “L”, the level of the clock signal φ_(1B) goes to “H”, and also thepotential at the node N₂₀₁ goes to “L” and the potential at the nodeN₂₀₂ goes to “H” (for a period of time of (V)), the transistor P₂₀₃ isturn on, and the node N₂₀₂ becomes conductive with the node N₂₀₃.Therefore, the potential difference between the source and the gate ofthe transistor P₂₀₁ becomes zero. At this time, although the potentialat the node N₂₀₁ becomes lower than that at the node N₂₀₂, no current iscaused to flow between the nodes N₂₀₂ and N₂₀₁ since the transistor P₂₀₁is turned off. In addition, the potential at the node N₂₀₂ becomeshigher than the potential existing when the transistor P₂₀₁ is in the onstate by about Vφ·C/(C+Cs) as shown in the expression (1), and thereforethe potential at the node N₂₀₂ becomes higher than the potentialexisting when the “H” state has been obtained.

The above-mentioned operation is also applied to the circuit blocksPCH₀₂ to PCH₀₄, and hence the output potential of the circuit blocklocated more backward stage or closer to the output terminal becomeshigher in the positive direction. That is, the semiconductor boostercircuit according to the seventh embodiment is the positive high voltagegenerating circuit employing the P-channel MOS transistors.

Incidentally, in the semiconductor booster circuit according to theseventh embodiment, for example, since the potential at the substrateterminal SUB₁ is higher than the potential at the sources or drains ofthe transistors P₂₀₁ and P₂₀₂, the absolute value of the thresholdvoltage is increased due to the substrate effect, and hence both thetransistors P₂₀₁ and P₂₀₂ are difficult to be turned on, or there is apossibility that the on-current becomes small. However, the wholesubstrate potentials are divided into the two potentials, i.e., thepotential at SUB₁ and the potential at SUB₂, whereby the increasing ofthe threshold voltage due to the substrate bias effect is reduced. Ifthe substrate potentials are divided into four blocks and the potentialof each block is controlled, the integration becomes poor but theincreasing of the threshold voltage due to the substrate bias effect canbe further reduced.

In the semiconductor booster circuit according to the seventhembodiment, since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage can be madesubstantially zero, the larger boosting capability is obtained ascompared with the sixth embodiment. In particular, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the difference inboosting capability between the sixth embodiment and the seventhembodiment becomes remarkably large. For example, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the number n of stagesof the booster circuit required for obtaining a desired output voltageneeds to be greatly increased in the booster circuit of the sixthembodiment due to the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage, but in thebooster circuit of the seventh embodiment, it is not required at all.For example, in the case where the power supply voltage Vdd is 2.0V, inthe sixth embodiment, the number of stages of the booster circuitrequired for obtaining the output voltage V_(POUT) of 23V is 20 whereasin the booster circuit of the seventh embodiment, the required number ofstages is only 12.

On the other hand, the booster circuit of the sixth embodiment isadvantageous as compared with the booster circuit of the seventhembodiment in that the configuration is simpler and also only two kindsof clock signals are enough.

Incidentally, it is to be understood that in the above-mentionedembodiments, the various changes may be made. For example, the number ofstages of the booster circuit is not limited to four in theabove-mentioned embodiment, and hence it may be set to any valuedetermined in accordance with the voltage to be boosted, the circuitscale and the like. In addition, the N-channel depletion type MOStransistors M₁₀₁ to M₁₀₈ are exemplarily employed as the transistorsconstituting the booster circuit in the sixth embodiment and also theP-channel MOS transistors P₂₀₁ to P₂₀₄ are exemplarily employed as thetransistors constituting the booster circuit in the seventh embodiment.However, as for those transistors, other transistors such as N-channelenhancement type MOS transistors may also be employed. For example, theN-channel MOS transistors M₁₀₁ to M₁₀₈ in the sixth embodiment may besubstituted by P-channel MOS transistors which are formed in the N typewell region, and also the power supply terminal N₁₂₀ may be grounded toprovide the negative high voltage generating circuit. In addition, theP-channel MOS transistors P₂₀₁ to P₂₀₄ in the seventh embodiment may besubstituted by N-channel MOS transistors which are formed in the P typewell region to provide the negative high voltage generating circuit.

In the sixth and seventh embodiments, the substrate terminals of the MOStransistors constituting the booster circuit are divided into thenecessary groups, and also are controlled to the different potentialsfor the groups, whereby it is possible to prevent the substrate biaseffect from occurring. Therefore, the high boosting capability can beobtained and also the increasing of the circuit area can be suppressedto the minimum.

What is claimed is:
 1. A semiconductor booster circuit, comprising: aplurality of stages each having a MOS transistor and a capacitor, saidMOS transistor being formed in a well and having a drain, a source and agate, and said capacitor having one terminal connected to the drain ofsaid MOS transistor; wherein said plurality of stages are connected inseries by connecting said MOS transistor of said plurality of stages incascade; a voltage is directly applied to the drain of said MOStransistor in a stage closest to an input terminal so that said voltageis boosted by said MOS transistor in each of said plurality of stagesthereby generating a boosted voltage, which is higher than said voltage,at the source of said MOS transistor in a stage closest to an outputterminal; wherein in each of said plurality of stages, the source ofsaid MOS transistor is directly connected to the gate of said MOStransistor and the well in which said MOS transistor is formed; andwells of said plurality of stages are electrically insulated from eachother.
 2. A semiconductor booster circuit according to claim 1, whereinthe wells of said plurality of stages are N-type wells formed in asemiconductor substrate, and are electrically insulated from each other;and said MOS transistor of said plurality of stages are P-channel MOStransistors formed in said N-type wells, respectively.
 3. Asemiconductor booster circuit having MOS transistors connected incascade, comprising: a plurality of stages each having a first MOStransistor, a second MOS transistor, a first capacitor having oneterminal that is connected to a drain of said first MOS transistor, anda second capacitor having one terminal that is connected to a drain ofsaid second MOS transistor; wherein in each of said stages, said firstand second MOS transistors are connected in series to constitute aplurality of series circuits; said series circuit that are constitutedin said plurality of stages, respectively, are connected in seriesbetween input and output sides of said plurality of stages; a voltage isdirectly applied to the drain of said first MOS transistor in the stageclosest to said input side so that said voltage is boosted by said firstand second MOS transistors in each of said stages thereby generating aboosted voltage, which is higher than said voltage, at the source ofsaid second MOS transistor in a stage closest to said output side; saidplurality of stages are divided into at least two groups; said first andsecond MOS transistors included in the stages of each group are formedin wells respective that are formed in a semiconductor substrate; andelectrical potentials respectively applied to said wells in said groupsare distinct from one another; a third capacitor having one terminalconnected to a gate of said first MOS transistor; a fourth capacitorhaving one terminal connected to a gate of said second MOS transistor; athird MOS transistor connected between the gate and a source of saidfirst MOS transistor, and having a gate connected to the one terminal ofsaid first capacitor; and a fourth MOS transistor connected between thegate and source of said second MOS transistor, and having a gateconnected to the one terminal of said second capacitor.
 4. Thesemiconductor booster circuit of claim 1, wherein said voltage is apower supply voltage.
 5. A semiconductor booster circuit according toclaim 3, wherein, in each stage, said wells in which said third andfourth MOS transistors are formed are electrically connected to saidwells in which said first and second MOS transistors are formed.
 6. Asemiconductor booster circuit according to claim 3, further comprisingmeans for inputting a pair of first clock signal that are in oppositephase with each other to other terminals of said first and secondcapacitors in each stage, respectively, and for inputting a pair ofsecond clock signals that are in opposite phase with each other to otherterminals of said third and fourth capacitors in each stage,respectively.
 7. The semiconductor booster circuit of claim 3, whereinsaid voltage is a power supply voltage.
 8. The semiconductor boostercircuit of claim 3, wherein said MOS transistors of said plurality ofstages are P-channel MOS transistors formed in N-type wells.
 9. Asemiconductor booster circuit, comprising: a plurality of stages eachhaving a MOS transistor and a capacitor, said MOS transistor beingformed in a well and having a drain, a source and a gate, and saidcapacitor having one terminal connected to the source of said MOStransistor; wherein said plurality of stages are connected in series byconnecting said MOS transistor of said plurality of stages in cascade; avoltage is directly applied to the source of said MOS transistor in astage closest to an input terminal so that said voltage is boosted bysaid MOS transistor in each of said plurality of stages therebygenerating a boosted voltage, which is higher than said voltage, at thedrain of said MOS transistor in a stage closest to an output terminal;wherein in each of said plurality of stages, the source of said MOStransistor is directly connected to the gate of said MOS transistor andthe well in which said MOS transistor is formed; and wells of saidplurality of stages are electrically insulated from each other.
 10. Asemiconductor booster circuit according to claim 8, wherein the wells ofsaid plurality of stages are P-type wells formed in a semiconductorsubstrate, and are electrically insulated from each other; and said MOStransistor of said plurality of stages are N-channel MOS transistorsformed in said P-type wells, respectively.
 11. The semiconductor boostercircuit of claim 9, wherein said voltage is a power supply voltage.